2019-03-25 11:41:34 +01:00
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/*
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*------------------------------------------------------------------
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* Copyright (c) 2018 Cisco and/or its affiliates.
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*------------------------------------------------------------------
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*/
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#include <unistd.h>
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#include <fcntl.h>
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#include <net/if.h>
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#include <linux/if_link.h>
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#include <linux/if_ether.h>
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#include <vppinfra/linux/sysfs.h>
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#include <vlib/vlib.h>
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#include <vlib/unix/unix.h>
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#include <vlib/pci/pci.h>
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#include <vnet/ethernet/ethernet.h>
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2020-11-25 14:44:37 +01:00
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#include <vnet/interface/rx_queue_funcs.h>
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2019-03-25 11:41:34 +01:00
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#include <rdma/rdma.h>
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2019-04-03 15:16:28 +02:00
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/* Default RSS hash key (from DPDK MLX driver) */
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static u8 rdma_rss_hash_key[] = {
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0x2c, 0xc6, 0x81, 0xd1,
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0x5b, 0xdb, 0xf4, 0xf7,
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0xfc, 0xa2, 0x83, 0x19,
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0xdb, 0x1a, 0x3e, 0x94,
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0x6b, 0x9e, 0x38, 0xd9,
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0x2c, 0x9c, 0x03, 0xd1,
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0xad, 0x99, 0x44, 0xa7,
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0xd9, 0x56, 0x3d, 0x59,
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0x06, 0x3c, 0x25, 0xf3,
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0xfc, 0x1f, 0xdc, 0x2a,
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};
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2019-03-25 11:41:34 +01:00
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rdma_main_t rdma_main;
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2021-02-12 17:55:38 +01:00
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/* (dev) is of type (rdma_device_t *) */
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#define rdma_log__(lvl, dev, f, ...) \
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do \
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{ \
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vlib_log ((lvl), rdma_main.log_class, "%s: " f, (dev)->name, \
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##__VA_ARGS__); \
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} \
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while (0)
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2019-05-22 18:09:19 +02:00
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#define rdma_log(lvl, dev, f, ...) \
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rdma_log__((lvl), (dev), "%s (%d): " f, strerror(errno), errno, ##__VA_ARGS__)
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static struct ibv_flow *
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rdma_rxq_init_flow (const rdma_device_t * rd, struct ibv_qp *qp,
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const mac_address_t * mac, const mac_address_t * mask,
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2020-10-16 17:12:41 +02:00
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u16 ether_type, u32 flags)
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2019-05-22 18:09:19 +02:00
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{
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struct ibv_flow *flow;
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struct raw_eth_flow_attr
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{
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struct ibv_flow_attr attr;
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struct ibv_flow_spec_eth spec_eth;
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} __attribute__ ((packed)) fa;
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memset (&fa, 0, sizeof (fa));
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fa.attr.num_of_specs = 1;
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fa.attr.port = 1;
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fa.attr.flags = flags;
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fa.spec_eth.type = IBV_FLOW_SPEC_ETH;
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fa.spec_eth.size = sizeof (struct ibv_flow_spec_eth);
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memcpy (fa.spec_eth.val.dst_mac, mac, sizeof (fa.spec_eth.val.dst_mac));
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memcpy (fa.spec_eth.mask.dst_mac, mask, sizeof (fa.spec_eth.mask.dst_mac));
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2020-10-16 17:12:41 +02:00
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if (ether_type)
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{
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fa.spec_eth.val.ether_type = ether_type;
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fa.spec_eth.mask.ether_type = 0xffff;
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}
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2019-05-22 18:09:19 +02:00
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flow = ibv_create_flow (qp, &fa.attr);
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if (!flow)
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rdma_log (VLIB_LOG_LEVEL_ERR, rd, "ibv_create_flow() failed");
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return flow;
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}
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static u32
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rdma_rxq_destroy_flow (const rdma_device_t * rd, struct ibv_flow **flow)
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{
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if (!*flow)
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return 0;
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if (ibv_destroy_flow (*flow))
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{
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rdma_log (VLIB_LOG_LEVEL_ERR, rd, "ibv_destroy_flow() failed");
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return ~0;
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}
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*flow = 0;
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return 0;
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}
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static u32
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rdma_dev_set_promisc (rdma_device_t * rd)
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{
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const mac_address_t all = {.bytes = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0} };
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int err;
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2020-10-16 17:12:41 +02:00
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err = rdma_rxq_destroy_flow (rd, &rd->flow_mcast6);
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err |= rdma_rxq_destroy_flow (rd, &rd->flow_ucast6);
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err |= rdma_rxq_destroy_flow (rd, &rd->flow_mcast4);
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err |= rdma_rxq_destroy_flow (rd, &rd->flow_ucast4);
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2019-05-22 18:09:19 +02:00
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if (err)
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return ~0;
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2020-10-16 17:12:41 +02:00
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rd->flow_ucast6 =
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rdma_rxq_init_flow (rd, rd->rx_qp6, &all, &all, ntohs (ETH_P_IPV6), 0);
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rd->flow_ucast4 = rdma_rxq_init_flow (rd, rd->rx_qp4, &all, &all, 0, 0);
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if (!rd->flow_ucast6 || !rd->flow_ucast4)
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2019-05-22 18:09:19 +02:00
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return ~0;
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rd->flags |= RDMA_DEVICE_F_PROMISC;
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return 0;
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}
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static u32
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rdma_dev_set_ucast (rdma_device_t * rd)
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{
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const mac_address_t ucast = {.bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
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};
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const mac_address_t mcast = {.bytes = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0} };
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int err;
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2020-10-16 17:12:41 +02:00
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err = rdma_rxq_destroy_flow (rd, &rd->flow_mcast6);
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err |= rdma_rxq_destroy_flow (rd, &rd->flow_ucast6);
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err |= rdma_rxq_destroy_flow (rd, &rd->flow_mcast4);
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err |= rdma_rxq_destroy_flow (rd, &rd->flow_ucast4);
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2019-05-22 18:09:19 +02:00
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if (err)
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return ~0;
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2020-10-16 17:12:41 +02:00
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rd->flow_ucast6 =
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rdma_rxq_init_flow (rd, rd->rx_qp6, &rd->hwaddr, &ucast,
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ntohs (ETH_P_IPV6), 0);
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rd->flow_mcast6 =
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rdma_rxq_init_flow (rd, rd->rx_qp6, &mcast, &mcast, ntohs (ETH_P_IPV6),
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IBV_FLOW_ATTR_FLAGS_DONT_TRAP
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/* let others receive mcast packet too (eg. Linux) */
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);
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rd->flow_ucast4 =
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rdma_rxq_init_flow (rd, rd->rx_qp4, &rd->hwaddr, &ucast, 0, 0);
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rd->flow_mcast4 =
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rdma_rxq_init_flow (rd, rd->rx_qp4, &mcast, &mcast, 0,
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IBV_FLOW_ATTR_FLAGS_DONT_TRAP
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/* let others receive mcast packet too (eg. Linux) */
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2019-05-22 18:09:19 +02:00
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);
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2020-10-16 17:12:41 +02:00
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if (!rd->flow_ucast6 || !rd->flow_mcast6 || !rd->flow_ucast4
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|| !rd->flow_mcast4)
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2019-05-22 18:09:19 +02:00
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return ~0;
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rd->flags &= ~RDMA_DEVICE_F_PROMISC;
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return 0;
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}
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2019-08-12 11:44:20 +02:00
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static clib_error_t *
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rdma_mac_change (vnet_hw_interface_t * hw, const u8 * old, const u8 * new)
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{
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rdma_main_t *rm = &rdma_main;
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rdma_device_t *rd = vec_elt_at_index (rm->devices, hw->dev_instance);
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mac_address_from_bytes (&rd->hwaddr, new);
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if (!(rd->flags & RDMA_DEVICE_F_PROMISC) && rdma_dev_set_ucast (rd))
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{
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mac_address_from_bytes (&rd->hwaddr, old);
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return clib_error_return_unix (0, "MAC update failed");
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}
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return 0;
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}
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2022-01-06 21:14:08 +01:00
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static clib_error_t *
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2022-01-17 14:49:17 +01:00
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rdma_set_max_frame_size (vnet_main_t *vnm, vnet_hw_interface_t *hw,
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u32 frame_size)
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2019-05-22 18:09:19 +02:00
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{
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2022-01-06 21:14:08 +01:00
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return vnet_error (VNET_ERR_UNSUPPORTED, 0);
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2019-05-22 18:09:19 +02:00
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}
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2019-03-25 11:41:34 +01:00
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static u32
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rdma_flag_change (vnet_main_t * vnm, vnet_hw_interface_t * hw, u32 flags)
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{
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rdma_main_t *rm = &rdma_main;
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2019-05-22 18:09:19 +02:00
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rdma_device_t *rd = vec_elt_at_index (rm->devices, hw->dev_instance);
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switch (flags)
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{
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2020-05-12 22:34:39 -04:00
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case ETHERNET_INTERFACE_FLAG_DEFAULT_L3:
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2019-05-22 18:09:19 +02:00
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return rdma_dev_set_ucast (rd);
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case ETHERNET_INTERFACE_FLAG_ACCEPT_ALL:
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return rdma_dev_set_promisc (rd);
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}
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rdma_log__ (VLIB_LOG_LEVEL_ERR, rd, "unknown flag %x requested", flags);
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return ~0;
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2019-03-25 11:41:34 +01:00
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}
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static void
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rdma_update_state (vnet_main_t * vnm, rdma_device_t * rd, int port)
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{
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struct ibv_port_attr attr;
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u32 width = 0;
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u32 speed = 0;
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if (ibv_query_port (rd->ctx, port, &attr))
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{
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vnet_hw_interface_set_link_speed (vnm, rd->hw_if_index, 0);
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vnet_hw_interface_set_flags (vnm, rd->hw_if_index, 0);
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return;
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}
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/* update state */
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switch (attr.state)
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{
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case IBV_PORT_ACTIVE: /* fallthrough */
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case IBV_PORT_ACTIVE_DEFER:
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rd->flags |= RDMA_DEVICE_F_LINK_UP;
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vnet_hw_interface_set_flags (vnm, rd->hw_if_index,
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VNET_HW_INTERFACE_FLAG_LINK_UP);
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break;
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default:
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rd->flags &= ~RDMA_DEVICE_F_LINK_UP;
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vnet_hw_interface_set_flags (vnm, rd->hw_if_index, 0);
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break;
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}
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/* update speed */
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switch (attr.active_width)
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{
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case 1:
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width = 1;
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break;
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case 2:
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width = 4;
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break;
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case 4:
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width = 8;
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break;
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case 8:
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width = 12;
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break;
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}
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switch (attr.active_speed)
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{
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case 1:
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speed = 2500000;
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break;
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case 2:
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speed = 5000000;
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break;
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case 4: /* fallthrough */
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case 8:
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speed = 10000000;
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break;
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case 16:
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speed = 14000000;
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break;
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case 32:
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speed = 25000000;
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break;
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}
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vnet_hw_interface_set_link_speed (vnm, rd->hw_if_index, width * speed);
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}
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static clib_error_t *
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rdma_async_event_error_ready (clib_file_t * f)
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{
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rdma_main_t *rm = &rdma_main;
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rdma_device_t *rd = vec_elt_at_index (rm->devices, f->private_data);
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2019-08-21 15:11:43 +02:00
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return clib_error_return (0, "RDMA: %s: async event error", rd->name);
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2019-03-25 11:41:34 +01:00
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}
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static clib_error_t *
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rdma_async_event_read_ready (clib_file_t * f)
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{
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vnet_main_t *vnm = vnet_get_main ();
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rdma_main_t *rm = &rdma_main;
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rdma_device_t *rd = vec_elt_at_index (rm->devices, f->private_data);
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int ret;
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|
|
struct ibv_async_event event;
|
|
|
|
|
ret = ibv_get_async_event (rd->ctx, &event);
|
|
|
|
|
if (ret < 0)
|
2019-05-22 18:09:19 +02:00
|
|
|
return clib_error_return_unix (0, "ibv_get_async_event() failed");
|
2019-03-25 11:41:34 +01:00
|
|
|
|
|
|
|
|
switch (event.event_type)
|
|
|
|
|
{
|
|
|
|
|
case IBV_EVENT_PORT_ACTIVE:
|
|
|
|
|
rdma_update_state (vnm, rd, event.element.port_num);
|
|
|
|
|
break;
|
|
|
|
|
case IBV_EVENT_PORT_ERR:
|
|
|
|
|
rdma_update_state (vnm, rd, event.element.port_num);
|
|
|
|
|
break;
|
|
|
|
|
case IBV_EVENT_DEVICE_FATAL:
|
|
|
|
|
rd->flags &= ~RDMA_DEVICE_F_LINK_UP;
|
|
|
|
|
vnet_hw_interface_set_flags (vnm, rd->hw_if_index, 0);
|
2019-08-21 15:11:43 +02:00
|
|
|
vlib_log_emerg (rm->log_class, "%s: fatal error", rd->name);
|
2019-03-25 11:41:34 +01:00
|
|
|
break;
|
|
|
|
|
default:
|
2021-03-17 14:41:33 +01:00
|
|
|
rdma_log__ (VLIB_LOG_LEVEL_ERR, rd, "unhandeld RDMA async event %d",
|
2019-05-22 18:09:19 +02:00
|
|
|
event.event_type);
|
2019-03-25 11:41:34 +01:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ibv_ack_async_event (&event);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static clib_error_t *
|
|
|
|
|
rdma_async_event_init (rdma_device_t * rd)
|
|
|
|
|
{
|
|
|
|
|
clib_file_t t = { 0 };
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
/* make RDMA async event fd non-blocking */
|
|
|
|
|
ret = fcntl (rd->ctx->async_fd, F_GETFL);
|
|
|
|
|
if (ret < 0)
|
2019-05-22 18:09:19 +02:00
|
|
|
return clib_error_return_unix (0, "fcntl(F_GETFL) failed");
|
|
|
|
|
|
2019-03-25 11:41:34 +01:00
|
|
|
ret = fcntl (rd->ctx->async_fd, F_SETFL, ret | O_NONBLOCK);
|
|
|
|
|
if (ret < 0)
|
2019-05-22 18:09:19 +02:00
|
|
|
return clib_error_return_unix (0, "fcntl(F_SETFL, O_NONBLOCK) failed");
|
2019-03-25 11:41:34 +01:00
|
|
|
|
|
|
|
|
/* register RDMA async event fd */
|
|
|
|
|
t.read_function = rdma_async_event_read_ready;
|
|
|
|
|
t.file_descriptor = rd->ctx->async_fd;
|
|
|
|
|
t.error_function = rdma_async_event_error_ready;
|
|
|
|
|
t.private_data = rd->dev_instance;
|
2019-09-30 16:43:25 +02:00
|
|
|
t.description = format (0, "%v async event", rd->name);
|
2019-03-25 11:41:34 +01:00
|
|
|
|
|
|
|
|
rd->async_event_clib_file_index = clib_file_add (&file_main, &t);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
rdma_async_event_cleanup (rdma_device_t * rd)
|
|
|
|
|
{
|
|
|
|
|
clib_file_del_by_index (&file_main, rd->async_event_clib_file_index);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static clib_error_t *
|
|
|
|
|
rdma_register_interface (vnet_main_t * vnm, rdma_device_t * rd)
|
|
|
|
|
{
|
2022-01-06 20:36:14 +01:00
|
|
|
vnet_eth_interface_registration_t eir = {};
|
2020-05-12 22:34:39 -04:00
|
|
|
|
2022-01-06 20:36:14 +01:00
|
|
|
eir.dev_class_index = rdma_device_class.index;
|
|
|
|
|
eir.dev_instance = rd->dev_instance;
|
|
|
|
|
eir.address = rd->hwaddr.bytes;
|
|
|
|
|
eir.cb.flag_change = rdma_flag_change;
|
2022-01-17 14:49:17 +01:00
|
|
|
eir.cb.set_max_frame_size = rdma_set_max_frame_size;
|
2022-01-06 20:36:14 +01:00
|
|
|
rd->hw_if_index = vnet_eth_register_interface (vnm, &eir);
|
2020-05-12 22:34:39 -04:00
|
|
|
/* Indicate ability to support L3 DMAC filtering and
|
|
|
|
|
* initialize interface to L3 non-promisc mode */
|
2022-01-05 01:52:38 +01:00
|
|
|
vnet_hw_if_set_caps (vnm, rd->hw_if_index, VNET_HW_IF_CAP_MAC_FILTER);
|
2020-05-12 22:34:39 -04:00
|
|
|
ethernet_set_flags (vnm, rd->hw_if_index,
|
|
|
|
|
ETHERNET_INTERFACE_FLAG_DEFAULT_L3);
|
2022-01-06 20:36:14 +01:00
|
|
|
return 0;
|
2019-03-25 11:41:34 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
rdma_unregister_interface (vnet_main_t * vnm, rdma_device_t * rd)
|
|
|
|
|
{
|
|
|
|
|
vnet_hw_interface_set_flags (vnm, rd->hw_if_index, 0);
|
|
|
|
|
ethernet_delete_interface (vnm, rd->hw_if_index);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
rdma_dev_cleanup (rdma_device_t * rd)
|
|
|
|
|
{
|
|
|
|
|
rdma_main_t *rm = &rdma_main;
|
|
|
|
|
rdma_rxq_t *rxq;
|
|
|
|
|
rdma_txq_t *txq;
|
|
|
|
|
|
|
|
|
|
#define _(fn, arg) if (arg) \
|
|
|
|
|
{ \
|
|
|
|
|
int rv; \
|
|
|
|
|
if ((rv = fn (arg))) \
|
2019-05-22 18:09:19 +02:00
|
|
|
rdma_log (VLIB_LOG_LEVEL_DEBUG, rd, #fn "() failed (rv = %d)", rv); \
|
2019-03-25 11:41:34 +01:00
|
|
|
}
|
|
|
|
|
|
2020-10-16 17:12:41 +02:00
|
|
|
_(ibv_destroy_flow, rd->flow_mcast6);
|
|
|
|
|
_(ibv_destroy_flow, rd->flow_ucast6);
|
|
|
|
|
_(ibv_destroy_flow, rd->flow_mcast4);
|
|
|
|
|
_(ibv_destroy_flow, rd->flow_ucast4);
|
2019-03-25 11:41:34 +01:00
|
|
|
_(ibv_dereg_mr, rd->mr);
|
|
|
|
|
vec_foreach (txq, rd->txqs)
|
|
|
|
|
{
|
|
|
|
|
_(ibv_destroy_qp, txq->qp);
|
|
|
|
|
_(ibv_destroy_cq, txq->cq);
|
|
|
|
|
}
|
|
|
|
|
vec_foreach (rxq, rd->rxqs)
|
|
|
|
|
{
|
2019-04-03 15:16:28 +02:00
|
|
|
_(ibv_destroy_wq, rxq->wq);
|
2019-03-25 11:41:34 +01:00
|
|
|
_(ibv_destroy_cq, rxq->cq);
|
|
|
|
|
}
|
2019-04-03 15:16:28 +02:00
|
|
|
_(ibv_destroy_rwq_ind_table, rd->rx_rwq_ind_tbl);
|
2020-10-16 17:12:41 +02:00
|
|
|
_(ibv_destroy_qp, rd->rx_qp6);
|
|
|
|
|
_(ibv_destroy_qp, rd->rx_qp4);
|
2019-03-25 11:41:34 +01:00
|
|
|
_(ibv_dealloc_pd, rd->pd);
|
|
|
|
|
_(ibv_close_device, rd->ctx);
|
|
|
|
|
#undef _
|
|
|
|
|
|
|
|
|
|
clib_error_free (rd->error);
|
|
|
|
|
|
|
|
|
|
vec_free (rd->rxqs);
|
|
|
|
|
vec_free (rd->txqs);
|
2019-03-28 23:34:56 +01:00
|
|
|
vec_free (rd->name);
|
2019-08-21 15:11:43 +02:00
|
|
|
vlib_pci_free_device_info (rd->pci);
|
2019-03-25 11:41:34 +01:00
|
|
|
pool_put (rm->devices, rd);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static clib_error_t *
|
2020-10-27 17:42:32 +01:00
|
|
|
rdma_rxq_init (vlib_main_t * vm, rdma_device_t * rd, u16 qid, u32 n_desc,
|
|
|
|
|
u8 no_multi_seg, u16 max_pktlen)
|
2019-03-25 11:41:34 +01:00
|
|
|
{
|
|
|
|
|
rdma_rxq_t *rxq;
|
2019-04-03 15:16:28 +02:00
|
|
|
struct ibv_wq_init_attr wqia;
|
2020-03-12 11:56:00 +01:00
|
|
|
struct ibv_cq_init_attr_ex cqa = { };
|
2019-04-03 15:16:28 +02:00
|
|
|
struct ibv_wq_attr wqa;
|
2020-03-12 11:56:00 +01:00
|
|
|
struct ibv_cq_ex *cqex;
|
2020-10-21 14:48:38 +02:00
|
|
|
struct mlx5dv_wq_init_attr dv_wqia = { };
|
2020-10-27 17:42:32 +01:00
|
|
|
int is_mlx5dv = ! !(rd->flags & RDMA_DEVICE_F_MLX5DV);
|
|
|
|
|
int is_striding = ! !(rd->flags & RDMA_DEVICE_F_STRIDING_RQ);
|
2019-03-25 11:41:34 +01:00
|
|
|
|
|
|
|
|
vec_validate_aligned (rd->rxqs, qid, CLIB_CACHE_LINE_BYTES);
|
|
|
|
|
rxq = vec_elt_at_index (rd->rxqs, qid);
|
|
|
|
|
rxq->size = n_desc;
|
2020-10-21 14:48:38 +02:00
|
|
|
rxq->log_wqe_sz = 0;
|
|
|
|
|
rxq->buf_sz = vlib_buffer_get_default_data_size (vm);
|
2019-08-21 15:11:43 +02:00
|
|
|
vec_validate_aligned (rxq->bufs, n_desc - 1, CLIB_CACHE_LINE_BYTES);
|
2019-03-25 11:41:34 +01:00
|
|
|
|
2020-03-12 11:56:00 +01:00
|
|
|
cqa.cqe = n_desc;
|
2020-10-27 17:42:32 +01:00
|
|
|
if (is_mlx5dv)
|
2020-03-12 11:56:00 +01:00
|
|
|
{
|
|
|
|
|
struct mlx5dv_cq_init_attr dvcq = { };
|
2022-12-30 20:04:39 +00:00
|
|
|
dvcq.comp_mask = MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE |
|
|
|
|
|
MLX5DV_CQ_INIT_ATTR_MASK_CQE_SIZE;
|
2020-03-12 11:56:00 +01:00
|
|
|
dvcq.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
|
2022-12-30 20:04:39 +00:00
|
|
|
dvcq.cqe_size = 64;
|
2020-03-12 11:56:00 +01:00
|
|
|
if ((cqex = mlx5dv_create_cq (rd->ctx, &cqa, &dvcq)) == 0)
|
|
|
|
|
return clib_error_return_unix (0, "Create mlx5dv rx CQ Failed");
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if ((cqex = ibv_create_cq_ex (rd->ctx, &cqa)) == 0)
|
|
|
|
|
return clib_error_return_unix (0, "Create CQ Failed");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
rxq->cq = ibv_cq_ex_to_cq (cqex);
|
2019-03-25 11:41:34 +01:00
|
|
|
|
2019-04-03 15:16:28 +02:00
|
|
|
memset (&wqia, 0, sizeof (wqia));
|
|
|
|
|
wqia.wq_type = IBV_WQT_RQ;
|
|
|
|
|
wqia.max_wr = n_desc;
|
|
|
|
|
wqia.max_sge = 1;
|
|
|
|
|
wqia.pd = rd->pd;
|
|
|
|
|
wqia.cq = rxq->cq;
|
2020-10-27 17:42:32 +01:00
|
|
|
if (is_mlx5dv)
|
2020-10-21 14:48:38 +02:00
|
|
|
{
|
2020-10-27 17:42:32 +01:00
|
|
|
if (is_striding)
|
2020-10-21 14:48:38 +02:00
|
|
|
{
|
|
|
|
|
/* In STRIDING_RQ mode, map a descriptor to a stride, not a full WQE buffer */
|
|
|
|
|
uword data_seg_log2_sz =
|
|
|
|
|
min_log2 (vlib_buffer_get_default_data_size (vm));
|
2020-10-27 17:42:32 +01:00
|
|
|
rxq->buf_sz = 1 << data_seg_log2_sz;
|
2020-10-21 14:48:38 +02:00
|
|
|
/* The trick is also to map a descriptor to a data segment in the WQE SG list
|
|
|
|
|
The number of strides per WQE and the size of a WQE (in 16-bytes words) both
|
|
|
|
|
must be powers of two.
|
|
|
|
|
Moreover, in striding RQ mode, WQEs must include the SRQ header, which occupies
|
|
|
|
|
one 16-bytes word. That is why WQEs have 2*RDMA_RXQ_MAX_CHAIN_SZ 16-bytes words:
|
|
|
|
|
- One for the SRQ Header
|
|
|
|
|
- RDMA_RXQ_MAX_CHAIN_SZ for the different data segments (each mapped to
|
|
|
|
|
a stride, and a vlib_buffer)
|
|
|
|
|
- RDMA_RXQ_MAX_CHAIN_SZ-1 null data segments
|
|
|
|
|
*/
|
2020-10-27 17:42:32 +01:00
|
|
|
int max_chain_log_sz =
|
|
|
|
|
max_pktlen ? max_log2 ((max_pktlen /
|
|
|
|
|
(rxq->buf_sz)) +
|
|
|
|
|
1) : RDMA_RXQ_MAX_CHAIN_LOG_SZ;
|
|
|
|
|
max_chain_log_sz = clib_max (max_chain_log_sz, 3);
|
|
|
|
|
wqia.max_sge = 1 << max_chain_log_sz;
|
2020-10-21 14:48:38 +02:00
|
|
|
dv_wqia.comp_mask = MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
|
|
|
|
|
dv_wqia.striding_rq_attrs.two_byte_shift_en = 0;
|
|
|
|
|
dv_wqia.striding_rq_attrs.single_wqe_log_num_of_strides =
|
2020-10-27 17:42:32 +01:00
|
|
|
max_chain_log_sz;
|
2020-10-21 14:48:38 +02:00
|
|
|
dv_wqia.striding_rq_attrs.single_stride_log_num_of_bytes =
|
|
|
|
|
data_seg_log2_sz;
|
2020-10-27 17:42:32 +01:00
|
|
|
wqia.max_wr >>= max_chain_log_sz;
|
|
|
|
|
rxq->log_wqe_sz = max_chain_log_sz + 1;
|
|
|
|
|
rxq->log_stride_per_wqe = max_chain_log_sz;
|
2020-10-21 14:48:38 +02:00
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2020-10-27 17:42:32 +01:00
|
|
|
/* In non STRIDING_RQ mode and if multiseg is not disabled, each WQE is a SG list of data
|
|
|
|
|
segments, each pointing to a vlib_buffer. */
|
|
|
|
|
if (no_multi_seg)
|
|
|
|
|
{
|
|
|
|
|
wqia.max_sge = 1;
|
|
|
|
|
rxq->log_wqe_sz = 0;
|
|
|
|
|
rxq->n_ds_per_wqe = 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
int max_chain_sz =
|
|
|
|
|
max_pktlen ? (max_pktlen /
|
|
|
|
|
(rxq->buf_sz)) +
|
|
|
|
|
1 : RDMA_RXQ_LEGACY_MODE_MAX_CHAIN_SZ;
|
|
|
|
|
int max_chain_log_sz = max_log2 (max_chain_sz);
|
|
|
|
|
wqia.max_sge = 1 << max_chain_log_sz;
|
|
|
|
|
rxq->log_wqe_sz = max_chain_log_sz;
|
|
|
|
|
rxq->n_ds_per_wqe = max_chain_sz;
|
|
|
|
|
}
|
|
|
|
|
|
2020-10-21 14:48:38 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((rxq->wq = mlx5dv_create_wq (rd->ctx, &wqia, &dv_wqia)))
|
|
|
|
|
{
|
|
|
|
|
rxq->wq->events_completed = 0;
|
|
|
|
|
pthread_mutex_init (&rxq->wq->mutex, NULL);
|
|
|
|
|
pthread_cond_init (&rxq->wq->cond, NULL);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
return clib_error_return_unix (0, "Create WQ Failed");
|
|
|
|
|
}
|
|
|
|
|
else if ((rxq->wq = ibv_create_wq (rd->ctx, &wqia)) == 0)
|
2019-04-03 15:16:28 +02:00
|
|
|
return clib_error_return_unix (0, "Create WQ Failed");
|
|
|
|
|
|
|
|
|
|
memset (&wqa, 0, sizeof (wqa));
|
|
|
|
|
wqa.attr_mask = IBV_WQ_ATTR_STATE;
|
|
|
|
|
wqa.wq_state = IBV_WQS_RDY;
|
|
|
|
|
if (ibv_modify_wq (rxq->wq, &wqa) != 0)
|
|
|
|
|
return clib_error_return_unix (0, "Modify WQ (RDY) Failed");
|
2019-03-25 11:41:34 +01:00
|
|
|
|
2020-10-27 17:42:32 +01:00
|
|
|
if (is_mlx5dv)
|
2020-03-12 11:56:00 +01:00
|
|
|
{
|
|
|
|
|
struct mlx5dv_obj obj = { };
|
|
|
|
|
struct mlx5dv_cq dv_cq;
|
|
|
|
|
struct mlx5dv_rwq dv_rwq;
|
|
|
|
|
u64 qw0;
|
2020-10-21 14:48:38 +02:00
|
|
|
u64 qw0_nullseg;
|
2020-10-27 17:42:32 +01:00
|
|
|
u32 wqe_sz_mask = (1 << rxq->log_wqe_sz) - 1;
|
2020-03-12 11:56:00 +01:00
|
|
|
|
|
|
|
|
obj.cq.in = rxq->cq;
|
|
|
|
|
obj.cq.out = &dv_cq;
|
|
|
|
|
obj.rwq.in = rxq->wq;
|
|
|
|
|
obj.rwq.out = &dv_rwq;
|
|
|
|
|
|
|
|
|
|
if ((mlx5dv_init_obj (&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_RWQ)))
|
|
|
|
|
return clib_error_return_unix (0, "mlx5dv: failed to init rx obj");
|
|
|
|
|
|
|
|
|
|
if (dv_cq.cqe_size != sizeof (mlx5dv_cqe_t))
|
|
|
|
|
return clib_error_return_unix (0, "mlx5dv: incompatible rx CQE size");
|
|
|
|
|
|
|
|
|
|
rxq->log2_cq_size = max_log2 (dv_cq.cqe_cnt);
|
|
|
|
|
rxq->cqes = (mlx5dv_cqe_t *) dv_cq.buf;
|
|
|
|
|
rxq->cq_db = (volatile u32 *) dv_cq.dbrec;
|
|
|
|
|
rxq->cqn = dv_cq.cqn;
|
|
|
|
|
|
2020-10-21 14:48:38 +02:00
|
|
|
rxq->wqes = (mlx5dv_wqe_ds_t *) dv_rwq.buf;
|
2020-03-12 11:56:00 +01:00
|
|
|
rxq->wq_db = (volatile u32 *) dv_rwq.dbrec;
|
|
|
|
|
rxq->wq_stride = dv_rwq.stride;
|
|
|
|
|
rxq->wqe_cnt = dv_rwq.wqe_cnt;
|
|
|
|
|
|
2020-10-21 14:48:38 +02:00
|
|
|
qw0 = clib_host_to_net_u32 (rxq->buf_sz);
|
|
|
|
|
qw0_nullseg = 0;
|
2020-03-12 11:56:00 +01:00
|
|
|
qw0 |= (u64) clib_host_to_net_u32 (rd->lkey) << 32;
|
2020-10-21 14:48:38 +02:00
|
|
|
qw0_nullseg |= (u64) clib_host_to_net_u32 (rd->lkey) << 32;
|
|
|
|
|
|
2020-10-27 17:42:32 +01:00
|
|
|
/* Prefill the different 16 bytes words of the WQ.
|
|
|
|
|
- If not in striding RQ mode, for each WQE, init with qw0 the first
|
|
|
|
|
RDMA_RXQ_LEGACY_MODE_MAX_CHAIN_SZ, and init the rest of the WQE
|
|
|
|
|
with null segments.
|
|
|
|
|
- If in striding RQ mode, for each WQE, the RDMA_RXQ_MAX_CHAIN_SZ + 1
|
|
|
|
|
first 16-bytes words are initialised with qw0, the rest are null segments */
|
|
|
|
|
|
2020-10-21 14:48:38 +02:00
|
|
|
for (int i = 0; i < rxq->wqe_cnt << rxq->log_wqe_sz; i++)
|
2020-10-27 17:42:32 +01:00
|
|
|
if ((!is_striding
|
|
|
|
|
&& ((i & wqe_sz_mask) < rxq->n_ds_per_wqe))
|
|
|
|
|
|| (is_striding
|
|
|
|
|
&& ((i == 0)
|
|
|
|
|
|| !(((i - 1) >> rxq->log_stride_per_wqe) & 0x1))))
|
2020-10-21 14:48:38 +02:00
|
|
|
rxq->wqes[i].dsz_and_lkey = qw0;
|
|
|
|
|
else
|
|
|
|
|
rxq->wqes[i].dsz_and_lkey = qw0_nullseg;
|
2020-03-12 11:56:00 +01:00
|
|
|
|
|
|
|
|
for (int i = 0; i < (1 << rxq->log2_cq_size); i++)
|
|
|
|
|
rxq->cqes[i].opcode_cqefmt_se_owner = 0xff;
|
2020-10-27 17:42:32 +01:00
|
|
|
|
|
|
|
|
if (!is_striding)
|
|
|
|
|
{
|
|
|
|
|
vec_validate_aligned (rxq->second_bufs, n_desc - 1,
|
|
|
|
|
CLIB_CACHE_LINE_BYTES);
|
|
|
|
|
vec_validate_aligned (rxq->n_used_per_chain, n_desc - 1,
|
|
|
|
|
CLIB_CACHE_LINE_BYTES);
|
|
|
|
|
rxq->n_total_additional_segs = n_desc * (rxq->n_ds_per_wqe - 1);
|
|
|
|
|
for (int i = 0; i < n_desc; i++)
|
|
|
|
|
rxq->n_used_per_chain[i] = rxq->n_ds_per_wqe - 1;
|
|
|
|
|
}
|
2020-03-12 11:56:00 +01:00
|
|
|
}
|
|
|
|
|
|
2019-04-03 15:16:28 +02:00
|
|
|
return 0;
|
|
|
|
|
}
|
2019-03-25 11:41:34 +01:00
|
|
|
|
2021-03-17 14:41:33 +01:00
|
|
|
static uint64_t
|
|
|
|
|
rdma_rss42ibv (const rdma_rss4_t rss4)
|
|
|
|
|
{
|
|
|
|
|
switch (rss4)
|
|
|
|
|
{
|
|
|
|
|
case RDMA_RSS4_IP:
|
|
|
|
|
return IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4;
|
|
|
|
|
case RDMA_RSS4_IP_UDP:
|
|
|
|
|
return IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4 |
|
|
|
|
|
IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP;
|
|
|
|
|
case RDMA_RSS4_AUTO: /* fallthrough */
|
|
|
|
|
case RDMA_RSS4_IP_TCP:
|
|
|
|
|
return IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4 |
|
|
|
|
|
IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP;
|
|
|
|
|
}
|
|
|
|
|
ASSERT (0);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint64_t
|
|
|
|
|
rdma_rss62ibv (const rdma_rss6_t rss6)
|
|
|
|
|
{
|
|
|
|
|
switch (rss6)
|
|
|
|
|
{
|
|
|
|
|
case RDMA_RSS6_IP:
|
|
|
|
|
return IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6;
|
|
|
|
|
case RDMA_RSS6_IP_UDP:
|
|
|
|
|
return IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6 |
|
|
|
|
|
IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP;
|
|
|
|
|
case RDMA_RSS6_AUTO: /* fallthrough */
|
|
|
|
|
case RDMA_RSS6_IP_TCP:
|
|
|
|
|
return IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6 |
|
|
|
|
|
IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP;
|
|
|
|
|
}
|
|
|
|
|
ASSERT (0);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-04-03 15:16:28 +02:00
|
|
|
static clib_error_t *
|
2021-03-17 14:41:33 +01:00
|
|
|
rdma_rxq_finalize (vlib_main_t *vm, rdma_device_t *rd)
|
2019-04-03 15:16:28 +02:00
|
|
|
{
|
|
|
|
|
struct ibv_rwq_ind_table_init_attr rwqia;
|
|
|
|
|
struct ibv_qp_init_attr_ex qpia;
|
|
|
|
|
struct ibv_wq **ind_tbl;
|
2021-05-03 17:02:39 +02:00
|
|
|
const u32 rxq_sz = vec_len (rd->rxqs);
|
|
|
|
|
u32 ind_tbl_sz = rxq_sz;
|
2019-04-03 15:16:28 +02:00
|
|
|
u32 i;
|
2019-03-25 11:41:34 +01:00
|
|
|
|
2021-05-03 17:02:39 +02:00
|
|
|
if (!is_pow2 (ind_tbl_sz))
|
|
|
|
|
{
|
|
|
|
|
/* in case we do not have a power-of-2 number of rxq, we try to use the
|
|
|
|
|
* maximum supported to minimize the imbalance */
|
|
|
|
|
struct ibv_device_attr_ex attr;
|
|
|
|
|
if (ibv_query_device_ex (rd->ctx, 0, &attr))
|
|
|
|
|
return clib_error_return_unix (0, "device query failed");
|
|
|
|
|
ind_tbl_sz = attr.rss_caps.max_rwq_indirection_table_size;
|
|
|
|
|
if (ind_tbl_sz < rxq_sz)
|
|
|
|
|
return clib_error_create ("too many rxqs requested (%d) compared to "
|
|
|
|
|
"max indirection table size (%d)",
|
|
|
|
|
rxq_sz, ind_tbl_sz);
|
|
|
|
|
}
|
2019-03-25 11:41:34 +01:00
|
|
|
|
2021-05-03 17:02:39 +02:00
|
|
|
ind_tbl = vec_new (struct ibv_wq *, ind_tbl_sz);
|
|
|
|
|
vec_foreach_index (i, ind_tbl)
|
|
|
|
|
vec_elt (ind_tbl, i) = vec_elt (rd->rxqs, i % rxq_sz).wq;
|
2019-04-03 15:16:28 +02:00
|
|
|
memset (&rwqia, 0, sizeof (rwqia));
|
2021-05-03 17:02:39 +02:00
|
|
|
ASSERT (is_pow2 (vec_len (ind_tbl)));
|
2019-04-03 15:16:28 +02:00
|
|
|
rwqia.log_ind_tbl_size = min_log2 (vec_len (ind_tbl));
|
|
|
|
|
rwqia.ind_tbl = ind_tbl;
|
|
|
|
|
if ((rd->rx_rwq_ind_tbl = ibv_create_rwq_ind_table (rd->ctx, &rwqia)) == 0)
|
|
|
|
|
return clib_error_return_unix (0, "RWQ indirection table create failed");
|
|
|
|
|
vec_free (ind_tbl);
|
|
|
|
|
|
|
|
|
|
memset (&qpia, 0, sizeof (qpia));
|
|
|
|
|
qpia.qp_type = IBV_QPT_RAW_PACKET;
|
|
|
|
|
qpia.comp_mask =
|
|
|
|
|
IBV_QP_INIT_ATTR_PD | IBV_QP_INIT_ATTR_IND_TABLE |
|
|
|
|
|
IBV_QP_INIT_ATTR_RX_HASH;
|
|
|
|
|
qpia.pd = rd->pd;
|
|
|
|
|
qpia.rwq_ind_tbl = rd->rx_rwq_ind_tbl;
|
|
|
|
|
STATIC_ASSERT_SIZEOF (rdma_rss_hash_key, 40);
|
|
|
|
|
qpia.rx_hash_conf.rx_hash_key_len = sizeof (rdma_rss_hash_key);
|
|
|
|
|
qpia.rx_hash_conf.rx_hash_key = rdma_rss_hash_key;
|
|
|
|
|
qpia.rx_hash_conf.rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ;
|
2020-10-16 17:12:41 +02:00
|
|
|
|
2021-03-17 14:41:33 +01:00
|
|
|
qpia.rx_hash_conf.rx_hash_fields_mask = rdma_rss42ibv (rd->rss4);
|
2020-10-16 17:12:41 +02:00
|
|
|
if ((rd->rx_qp4 = ibv_create_qp_ex (rd->ctx, &qpia)) == 0)
|
|
|
|
|
return clib_error_return_unix (0, "IPv4 Queue Pair create failed");
|
|
|
|
|
|
2021-03-17 14:41:33 +01:00
|
|
|
qpia.rx_hash_conf.rx_hash_fields_mask = rdma_rss62ibv (rd->rss6);
|
2020-10-16 17:12:41 +02:00
|
|
|
if ((rd->rx_qp6 = ibv_create_qp_ex (rd->ctx, &qpia)) == 0)
|
|
|
|
|
return clib_error_return_unix (0, "IPv6 Queue Pair create failed");
|
2019-04-03 15:16:28 +02:00
|
|
|
|
2019-05-22 18:09:19 +02:00
|
|
|
if (rdma_dev_set_ucast (rd))
|
|
|
|
|
return clib_error_return_unix (0, "Set unicast mode failed");
|
|
|
|
|
|
|
|
|
|
return 0;
|
2019-03-25 11:41:34 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static clib_error_t *
|
|
|
|
|
rdma_txq_init (vlib_main_t * vm, rdma_device_t * rd, u16 qid, u32 n_desc)
|
|
|
|
|
{
|
|
|
|
|
rdma_txq_t *txq;
|
|
|
|
|
struct ibv_qp_init_attr qpia;
|
|
|
|
|
struct ibv_qp_attr qpa;
|
|
|
|
|
int qp_flags;
|
2022-12-30 20:04:39 +00:00
|
|
|
int is_mlx5dv = !!(rd->flags & RDMA_DEVICE_F_MLX5DV);
|
2019-03-25 11:41:34 +01:00
|
|
|
|
|
|
|
|
vec_validate_aligned (rd->txqs, qid, CLIB_CACHE_LINE_BYTES);
|
|
|
|
|
txq = vec_elt_at_index (rd->txqs, qid);
|
2019-12-16 10:42:25 +01:00
|
|
|
ASSERT (is_pow2 (n_desc));
|
|
|
|
|
txq->bufs_log2sz = min_log2 (n_desc);
|
2019-08-21 15:11:43 +02:00
|
|
|
vec_validate_aligned (txq->bufs, n_desc - 1, CLIB_CACHE_LINE_BYTES);
|
2022-12-30 20:04:39 +00:00
|
|
|
if (is_mlx5dv)
|
|
|
|
|
{
|
|
|
|
|
struct ibv_cq_init_attr_ex cqa = {};
|
|
|
|
|
struct ibv_cq_ex *cqex;
|
|
|
|
|
struct mlx5dv_cq_init_attr dvcq = {};
|
2023-03-20 16:58:14 +08:00
|
|
|
dvcq.comp_mask = MLX5DV_CQ_INIT_ATTR_MASK_CQE_SIZE;
|
2022-12-30 20:04:39 +00:00
|
|
|
dvcq.cqe_size = 64;
|
|
|
|
|
cqa.cqe = n_desc;
|
|
|
|
|
if ((cqex = mlx5dv_create_cq (rd->ctx, &cqa, &dvcq)) == 0)
|
|
|
|
|
return clib_error_return_unix (0, "Create mlx5dv tx CQ Failed");
|
|
|
|
|
txq->cq = ibv_cq_ex_to_cq (cqex);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if ((txq->cq = ibv_create_cq (rd->ctx, n_desc, NULL, NULL, 0)) == 0)
|
|
|
|
|
return clib_error_return_unix (0, "Create CQ Failed");
|
|
|
|
|
}
|
2019-03-25 11:41:34 +01:00
|
|
|
|
|
|
|
|
memset (&qpia, 0, sizeof (qpia));
|
|
|
|
|
qpia.send_cq = txq->cq;
|
|
|
|
|
qpia.recv_cq = txq->cq;
|
|
|
|
|
qpia.cap.max_send_wr = n_desc;
|
|
|
|
|
qpia.cap.max_send_sge = 1;
|
2019-04-03 16:03:37 +02:00
|
|
|
qpia.qp_type = IBV_QPT_RAW_PACKET;
|
2019-03-25 11:41:34 +01:00
|
|
|
|
|
|
|
|
if ((txq->qp = ibv_create_qp (rd->pd, &qpia)) == 0)
|
|
|
|
|
return clib_error_return_unix (0, "Queue Pair create failed");
|
|
|
|
|
|
|
|
|
|
memset (&qpa, 0, sizeof (qpa));
|
|
|
|
|
qp_flags = IBV_QP_STATE | IBV_QP_PORT;
|
|
|
|
|
qpa.qp_state = IBV_QPS_INIT;
|
|
|
|
|
qpa.port_num = 1;
|
|
|
|
|
if (ibv_modify_qp (txq->qp, &qpa, qp_flags) != 0)
|
|
|
|
|
return clib_error_return_unix (0, "Modify QP (init) Failed");
|
|
|
|
|
|
|
|
|
|
memset (&qpa, 0, sizeof (qpa));
|
|
|
|
|
qp_flags = IBV_QP_STATE;
|
|
|
|
|
qpa.qp_state = IBV_QPS_RTR;
|
|
|
|
|
if (ibv_modify_qp (txq->qp, &qpa, qp_flags) != 0)
|
|
|
|
|
return clib_error_return_unix (0, "Modify QP (receive) Failed");
|
|
|
|
|
|
|
|
|
|
memset (&qpa, 0, sizeof (qpa));
|
|
|
|
|
qp_flags = IBV_QP_STATE;
|
|
|
|
|
qpa.qp_state = IBV_QPS_RTS;
|
|
|
|
|
if (ibv_modify_qp (txq->qp, &qpa, qp_flags) != 0)
|
|
|
|
|
return clib_error_return_unix (0, "Modify QP (send) Failed");
|
2019-12-16 10:42:25 +01:00
|
|
|
|
|
|
|
|
txq->ibv_cq = txq->cq;
|
|
|
|
|
txq->ibv_qp = txq->qp;
|
|
|
|
|
|
|
|
|
|
if (rd->flags & RDMA_DEVICE_F_MLX5DV)
|
|
|
|
|
{
|
|
|
|
|
rdma_mlx5_wqe_t *tmpl = (void *) txq->dv_wqe_tmpl;
|
|
|
|
|
struct mlx5dv_cq dv_cq;
|
|
|
|
|
struct mlx5dv_qp dv_qp;
|
|
|
|
|
struct mlx5dv_obj obj = { };
|
|
|
|
|
|
|
|
|
|
obj.cq.in = txq->cq;
|
|
|
|
|
obj.cq.out = &dv_cq;
|
|
|
|
|
obj.qp.in = txq->qp;
|
|
|
|
|
obj.qp.out = &dv_qp;
|
|
|
|
|
|
|
|
|
|
if (mlx5dv_init_obj (&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP))
|
|
|
|
|
return clib_error_return_unix (0, "DV init obj failed");
|
|
|
|
|
|
|
|
|
|
if (RDMA_TXQ_BUF_SZ (txq) > dv_qp.sq.wqe_cnt
|
|
|
|
|
|| !is_pow2 (dv_qp.sq.wqe_cnt)
|
|
|
|
|
|| sizeof (rdma_mlx5_wqe_t) != dv_qp.sq.stride
|
|
|
|
|
|| (uword) dv_qp.sq.buf % sizeof (rdma_mlx5_wqe_t))
|
|
|
|
|
return clib_error_return (0, "Unsupported DV SQ parameters");
|
|
|
|
|
|
|
|
|
|
if (RDMA_TXQ_BUF_SZ (txq) > dv_cq.cqe_cnt
|
|
|
|
|
|| !is_pow2 (dv_cq.cqe_cnt)
|
|
|
|
|
|| sizeof (struct mlx5_cqe64) != dv_cq.cqe_size
|
|
|
|
|
|| (uword) dv_cq.buf % sizeof (struct mlx5_cqe64))
|
|
|
|
|
return clib_error_return (0, "Unsupported DV CQ parameters");
|
|
|
|
|
|
|
|
|
|
/* get SQ and doorbell addresses */
|
|
|
|
|
txq->dv_sq_wqes = dv_qp.sq.buf;
|
|
|
|
|
txq->dv_sq_dbrec = dv_qp.dbrec;
|
|
|
|
|
txq->dv_sq_db = dv_qp.bf.reg;
|
|
|
|
|
txq->dv_sq_log2sz = min_log2 (dv_qp.sq.wqe_cnt);
|
|
|
|
|
|
|
|
|
|
/* get CQ and doorbell addresses */
|
|
|
|
|
txq->dv_cq_cqes = dv_cq.buf;
|
|
|
|
|
txq->dv_cq_dbrec = dv_cq.dbrec;
|
|
|
|
|
txq->dv_cq_log2sz = min_log2 (dv_cq.cqe_cnt);
|
|
|
|
|
|
|
|
|
|
/* init tx desc template */
|
|
|
|
|
STATIC_ASSERT_SIZEOF (txq->dv_wqe_tmpl, sizeof (*tmpl));
|
|
|
|
|
mlx5dv_set_ctrl_seg (&tmpl->ctrl, 0, MLX5_OPCODE_SEND, 0,
|
|
|
|
|
txq->qp->qp_num, 0, RDMA_MLX5_WQE_DS, 0,
|
|
|
|
|
RDMA_TXQ_DV_INVALID_ID);
|
2020-03-16 14:44:10 +01:00
|
|
|
tmpl->eseg.inline_hdr_sz = htobe16 (MLX5_ETH_L2_INLINE_HEADER_SIZE);
|
2019-12-16 10:42:25 +01:00
|
|
|
mlx5dv_set_data_seg (&tmpl->dseg, 0, rd->lkey, 0);
|
|
|
|
|
}
|
|
|
|
|
|
2019-03-25 11:41:34 +01:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static clib_error_t *
|
2020-10-27 17:42:32 +01:00
|
|
|
rdma_dev_init (vlib_main_t * vm, rdma_device_t * rd,
|
|
|
|
|
rdma_create_if_args_t * args)
|
2019-03-25 11:41:34 +01:00
|
|
|
{
|
|
|
|
|
clib_error_t *err;
|
|
|
|
|
vlib_buffer_main_t *bm = vm->buffer_main;
|
|
|
|
|
vlib_thread_main_t *tm = vlib_get_thread_main ();
|
2020-10-27 17:42:32 +01:00
|
|
|
u32 rxq_num = args->rxq_num;
|
|
|
|
|
u32 rxq_size = args->rxq_size;
|
|
|
|
|
u32 txq_size = args->txq_size;
|
2019-04-03 15:16:28 +02:00
|
|
|
u32 i;
|
2019-03-25 11:41:34 +01:00
|
|
|
|
|
|
|
|
if (rd->ctx == 0)
|
|
|
|
|
return clib_error_return_unix (0, "Device Open Failed");
|
|
|
|
|
|
|
|
|
|
if ((rd->pd = ibv_alloc_pd (rd->ctx)) == 0)
|
|
|
|
|
return clib_error_return_unix (0, "PD Alloc Failed");
|
|
|
|
|
|
2019-12-16 10:42:25 +01:00
|
|
|
if ((rd->mr = ibv_reg_mr (rd->pd, (void *) bm->buffer_mem_start,
|
|
|
|
|
bm->buffer_mem_size,
|
|
|
|
|
IBV_ACCESS_LOCAL_WRITE)) == 0)
|
|
|
|
|
return clib_error_return_unix (0, "Register MR Failed");
|
|
|
|
|
|
|
|
|
|
rd->lkey = rd->mr->lkey; /* avoid indirection in datapath */
|
|
|
|
|
|
2019-04-03 15:16:28 +02:00
|
|
|
ethernet_mac_address_generate (rd->hwaddr.bytes);
|
|
|
|
|
|
2021-03-17 14:41:33 +01:00
|
|
|
rd->rss4 = args->rss4;
|
|
|
|
|
rd->rss6 = args->rss6;
|
|
|
|
|
|
2019-10-04 15:28:12 +02:00
|
|
|
/*
|
|
|
|
|
* /!\ WARNING /!\ creation order is important
|
|
|
|
|
* We *must* create TX queues *before* RX queues, otherwise we will receive
|
|
|
|
|
* the broacast packets we sent
|
|
|
|
|
*/
|
|
|
|
|
for (i = 0; i < tm->n_vlib_mains; i++)
|
|
|
|
|
if ((err = rdma_txq_init (vm, rd, i, txq_size)))
|
|
|
|
|
return err;
|
|
|
|
|
|
2019-04-03 15:16:28 +02:00
|
|
|
for (i = 0; i < rxq_num; i++)
|
2020-10-27 17:42:32 +01:00
|
|
|
if ((err =
|
|
|
|
|
rdma_rxq_init (vm, rd, i, rxq_size,
|
|
|
|
|
args->no_multi_seg, args->max_pktlen)))
|
2019-04-03 15:16:28 +02:00
|
|
|
return err;
|
|
|
|
|
if ((err = rdma_rxq_finalize (vm, rd)))
|
2019-03-25 11:41:34 +01:00
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uword
|
|
|
|
|
sysfs_path_to_pci_addr (char *path, vlib_pci_addr_t * addr)
|
|
|
|
|
{
|
|
|
|
|
uword rv;
|
|
|
|
|
unformat_input_t in;
|
|
|
|
|
u8 *s;
|
|
|
|
|
|
2023-08-07 01:07:09 +02:00
|
|
|
s = clib_file_get_resolved_basename (path);
|
2019-10-07 15:36:10 +02:00
|
|
|
if (!s)
|
|
|
|
|
return 0;
|
|
|
|
|
|
2019-03-25 11:41:34 +01:00
|
|
|
unformat_init_string (&in, (char *) s, strlen ((char *) s));
|
|
|
|
|
rv = unformat (&in, "%U", unformat_vlib_pci_addr, addr);
|
|
|
|
|
unformat_free (&in);
|
|
|
|
|
vec_free (s);
|
|
|
|
|
return rv;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
rdma_create_if (vlib_main_t * vm, rdma_create_if_args_t * args)
|
|
|
|
|
{
|
|
|
|
|
vnet_main_t *vnm = vnet_get_main ();
|
|
|
|
|
rdma_main_t *rm = &rdma_main;
|
2019-08-21 15:11:43 +02:00
|
|
|
rdma_device_t *rd;
|
|
|
|
|
vlib_pci_addr_t pci_addr;
|
|
|
|
|
struct ibv_device **dev_list;
|
2019-03-25 11:41:34 +01:00
|
|
|
int n_devs;
|
2019-08-21 15:11:43 +02:00
|
|
|
u8 *s;
|
2019-04-03 15:16:28 +02:00
|
|
|
u16 qid;
|
2019-08-21 15:11:43 +02:00
|
|
|
int i;
|
2019-04-03 15:16:28 +02:00
|
|
|
|
2020-01-07 16:08:43 +01:00
|
|
|
args->rxq_size = args->rxq_size ? args->rxq_size : 1024;
|
|
|
|
|
args->txq_size = args->txq_size ? args->txq_size : 1024;
|
2020-10-27 17:42:32 +01:00
|
|
|
args->rxq_num = args->rxq_num ? args->rxq_num : 2;
|
2019-04-03 15:16:28 +02:00
|
|
|
|
2019-08-21 15:11:43 +02:00
|
|
|
if (args->rxq_size < VLIB_FRAME_SIZE || args->txq_size < VLIB_FRAME_SIZE ||
|
2019-12-16 10:42:25 +01:00
|
|
|
args->rxq_size > 65535 || args->txq_size > 65535 ||
|
2019-08-21 15:11:43 +02:00
|
|
|
!is_pow2 (args->rxq_size) || !is_pow2 (args->txq_size))
|
2019-04-03 15:16:28 +02:00
|
|
|
{
|
|
|
|
|
args->rv = VNET_API_ERROR_INVALID_VALUE;
|
2021-03-17 14:41:33 +01:00
|
|
|
args->error = clib_error_return (0,
|
|
|
|
|
"queue size must be a power of two "
|
|
|
|
|
"between %d and 65535",
|
2019-12-16 10:42:25 +01:00
|
|
|
VLIB_FRAME_SIZE);
|
2019-08-21 15:11:43 +02:00
|
|
|
goto err0;
|
2019-04-03 15:16:28 +02:00
|
|
|
}
|
2019-03-25 11:41:34 +01:00
|
|
|
|
2019-08-21 15:11:43 +02:00
|
|
|
dev_list = ibv_get_device_list (&n_devs);
|
|
|
|
|
if (n_devs == 0)
|
2019-03-25 11:41:34 +01:00
|
|
|
{
|
|
|
|
|
args->error =
|
2019-08-21 15:11:43 +02:00
|
|
|
clib_error_return_unix (0,
|
|
|
|
|
"no RDMA devices available. Is the ib_uverbs module loaded?");
|
2019-03-25 11:41:34 +01:00
|
|
|
goto err0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-08-21 15:11:43 +02:00
|
|
|
/* get PCI address */
|
|
|
|
|
s = format (0, "/sys/class/net/%s/device%c", args->ifname, 0);
|
|
|
|
|
if (sysfs_path_to_pci_addr ((char *) s, &pci_addr) == 0)
|
2019-03-25 11:41:34 +01:00
|
|
|
{
|
2019-08-21 15:11:43 +02:00
|
|
|
args->error =
|
|
|
|
|
clib_error_return (0, "cannot find PCI address for device ");
|
|
|
|
|
goto err1;
|
2019-03-25 11:41:34 +01:00
|
|
|
}
|
|
|
|
|
|
2019-08-21 15:11:43 +02:00
|
|
|
pool_get_zero (rm->devices, rd);
|
|
|
|
|
rd->dev_instance = rd - rm->devices;
|
|
|
|
|
rd->per_interface_next_index = VNET_DEVICE_INPUT_NEXT_ETHERNET_INPUT;
|
|
|
|
|
rd->linux_ifname = format (0, "%s", args->ifname);
|
|
|
|
|
|
2019-11-06 17:24:51 +01:00
|
|
|
if (!args->name || 0 == args->name[0])
|
|
|
|
|
rd->name = format (0, "%s/%d", args->ifname, rd->dev_instance);
|
|
|
|
|
else
|
|
|
|
|
rd->name = format (0, "%s", args->name);
|
|
|
|
|
|
2019-08-21 15:11:43 +02:00
|
|
|
rd->pci = vlib_pci_get_device_info (vm, &pci_addr, &args->error);
|
|
|
|
|
if (!rd->pci)
|
|
|
|
|
goto err2;
|
2019-10-07 15:57:32 +02:00
|
|
|
|
|
|
|
|
/* if we failed to parse NUMA node, default to 0 */
|
|
|
|
|
if (-1 == rd->pci->numa_node)
|
|
|
|
|
rd->pci->numa_node = 0;
|
|
|
|
|
|
2019-08-21 15:11:43 +02:00
|
|
|
rd->pool = vlib_buffer_pool_get_default_for_numa (vm, rd->pci->numa_node);
|
|
|
|
|
|
|
|
|
|
if (strncmp ((char *) rd->pci->driver_name, "mlx5_core", 9))
|
2019-03-25 11:41:34 +01:00
|
|
|
{
|
|
|
|
|
args->error =
|
2019-08-21 15:11:43 +02:00
|
|
|
clib_error_return (0,
|
|
|
|
|
"invalid interface (only mlx5 supported for now)");
|
|
|
|
|
goto err2;
|
2019-03-25 11:41:34 +01:00
|
|
|
}
|
|
|
|
|
|
2019-08-21 15:11:43 +02:00
|
|
|
for (i = 0; i < n_devs; i++)
|
2019-03-25 11:41:34 +01:00
|
|
|
{
|
|
|
|
|
vlib_pci_addr_t addr;
|
|
|
|
|
|
|
|
|
|
vec_reset_length (s);
|
|
|
|
|
s = format (s, "%s/device%c", dev_list[i]->dev_path, 0);
|
|
|
|
|
|
|
|
|
|
if (sysfs_path_to_pci_addr ((char *) s, &addr) == 0)
|
|
|
|
|
continue;
|
|
|
|
|
|
2019-08-21 15:11:43 +02:00
|
|
|
if (addr.as_u32 != rd->pci->addr.as_u32)
|
2019-03-25 11:41:34 +01:00
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if ((rd->ctx = ibv_open_device (dev_list[i])))
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2020-03-12 11:56:00 +01:00
|
|
|
if (args->mode != RDMA_MODE_IBV)
|
|
|
|
|
{
|
|
|
|
|
struct mlx5dv_context mlx5dv_attrs = { };
|
2020-10-21 14:48:38 +02:00
|
|
|
mlx5dv_attrs.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
|
2020-03-12 11:56:00 +01:00
|
|
|
|
|
|
|
|
if (mlx5dv_query_device (rd->ctx, &mlx5dv_attrs) == 0)
|
|
|
|
|
{
|
2020-10-21 14:48:38 +02:00
|
|
|
uword data_seg_log2_sz =
|
|
|
|
|
min_log2 (vlib_buffer_get_default_data_size (vm));
|
|
|
|
|
|
2020-03-12 11:56:00 +01:00
|
|
|
if ((mlx5dv_attrs.flags & MLX5DV_CONTEXT_FLAGS_CQE_V1))
|
|
|
|
|
rd->flags |= RDMA_DEVICE_F_MLX5DV;
|
2020-10-21 14:48:38 +02:00
|
|
|
|
2020-10-27 17:42:32 +01:00
|
|
|
/* Enable striding RQ if neither multiseg nor striding rq
|
|
|
|
|
are explicitly disabled, and if the interface supports it.*/
|
|
|
|
|
if (!args->no_multi_seg && !args->disable_striding_rq
|
|
|
|
|
&& data_seg_log2_sz <=
|
2020-10-21 14:48:38 +02:00
|
|
|
mlx5dv_attrs.striding_rq_caps.max_single_stride_log_num_of_bytes
|
|
|
|
|
&& data_seg_log2_sz >=
|
|
|
|
|
mlx5dv_attrs.striding_rq_caps.min_single_stride_log_num_of_bytes
|
|
|
|
|
&& RDMA_RXQ_MAX_CHAIN_LOG_SZ >=
|
|
|
|
|
mlx5dv_attrs.striding_rq_caps.min_single_wqe_log_num_of_strides
|
|
|
|
|
&& RDMA_RXQ_MAX_CHAIN_LOG_SZ <=
|
|
|
|
|
mlx5dv_attrs.striding_rq_caps.max_single_wqe_log_num_of_strides)
|
|
|
|
|
rd->flags |= RDMA_DEVICE_F_STRIDING_RQ;
|
2020-03-12 11:56:00 +01:00
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (args->mode == RDMA_MODE_DV)
|
|
|
|
|
{
|
|
|
|
|
args->error = clib_error_return (0, "Direct Verbs mode not "
|
|
|
|
|
"supported on this interface");
|
|
|
|
|
goto err2;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2020-10-27 17:42:32 +01:00
|
|
|
if ((args->error = rdma_dev_init (vm, rd, args)))
|
2019-08-21 15:11:43 +02:00
|
|
|
goto err2;
|
2019-03-25 11:41:34 +01:00
|
|
|
|
|
|
|
|
if ((args->error = rdma_register_interface (vnm, rd)))
|
|
|
|
|
goto err2;
|
|
|
|
|
|
|
|
|
|
if ((args->error = rdma_async_event_init (rd)))
|
|
|
|
|
goto err3;
|
|
|
|
|
|
|
|
|
|
rdma_update_state (vnm, rd, 1);
|
|
|
|
|
|
|
|
|
|
vnet_sw_interface_t *sw = vnet_get_hw_sw_interface (vnm, rd->hw_if_index);
|
|
|
|
|
args->sw_if_index = rd->sw_if_index = sw->sw_if_index;
|
|
|
|
|
/*
|
|
|
|
|
* FIXME: add support for interrupt mode
|
|
|
|
|
* vnet_hw_interface_t *hw = vnet_get_hw_interface (vnm, rd->hw_if_index);
|
2022-01-05 01:52:38 +01:00
|
|
|
* hw->caps |= VNET_HW_IF_CAP_INT_MODE;
|
2019-03-25 11:41:34 +01:00
|
|
|
*/
|
2020-11-25 14:44:37 +01:00
|
|
|
vnet_hw_if_set_input_node (vnm, rd->hw_if_index, rdma_input_node.index);
|
2019-08-21 15:11:43 +02:00
|
|
|
|
2020-11-25 14:44:37 +01:00
|
|
|
vec_foreach_index (qid, rd->rxqs)
|
|
|
|
|
{
|
|
|
|
|
u32 queue_index = vnet_hw_if_register_rx_queue (
|
|
|
|
|
vnm, rd->hw_if_index, qid, VNET_HW_IF_RXQ_THREAD_ANY);
|
|
|
|
|
rd->rxqs[qid].queue_index = queue_index;
|
|
|
|
|
}
|
|
|
|
|
vnet_hw_if_update_runtime_data (vnm, rd->hw_if_index);
|
2019-08-21 15:11:43 +02:00
|
|
|
vec_free (s);
|
2019-03-25 11:41:34 +01:00
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
err3:
|
|
|
|
|
rdma_unregister_interface (vnm, rd);
|
|
|
|
|
err2:
|
|
|
|
|
rdma_dev_cleanup (rd);
|
|
|
|
|
err1:
|
|
|
|
|
ibv_free_device_list (dev_list);
|
|
|
|
|
vec_free (s);
|
|
|
|
|
args->rv = VNET_API_ERROR_INVALID_INTERFACE;
|
2019-08-21 15:11:43 +02:00
|
|
|
err0:
|
2019-03-25 11:41:34 +01:00
|
|
|
vlib_log_err (rm->log_class, "%U", format_clib_error, args->error);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
rdma_delete_if (vlib_main_t * vm, rdma_device_t * rd)
|
|
|
|
|
{
|
|
|
|
|
rdma_async_event_cleanup (rd);
|
|
|
|
|
rdma_unregister_interface (vnet_get_main (), rd);
|
|
|
|
|
rdma_dev_cleanup (rd);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static clib_error_t *
|
|
|
|
|
rdma_interface_admin_up_down (vnet_main_t * vnm, u32 hw_if_index, u32 flags)
|
|
|
|
|
{
|
|
|
|
|
vnet_hw_interface_t *hi = vnet_get_hw_interface (vnm, hw_if_index);
|
|
|
|
|
rdma_main_t *rm = &rdma_main;
|
|
|
|
|
rdma_device_t *rd = vec_elt_at_index (rm->devices, hi->dev_instance);
|
|
|
|
|
uword is_up = (flags & VNET_SW_INTERFACE_FLAG_ADMIN_UP) != 0;
|
|
|
|
|
|
|
|
|
|
if (rd->flags & RDMA_DEVICE_F_ERROR)
|
|
|
|
|
return clib_error_return (0, "device is in error state");
|
|
|
|
|
|
|
|
|
|
if (is_up)
|
|
|
|
|
{
|
|
|
|
|
vnet_hw_interface_set_flags (vnm, rd->hw_if_index,
|
|
|
|
|
VNET_HW_INTERFACE_FLAG_LINK_UP);
|
|
|
|
|
rd->flags |= RDMA_DEVICE_F_ADMIN_UP;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
vnet_hw_interface_set_flags (vnm, rd->hw_if_index, 0);
|
|
|
|
|
rd->flags &= ~RDMA_DEVICE_F_ADMIN_UP;
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
rdma_set_interface_next_node (vnet_main_t * vnm, u32 hw_if_index,
|
|
|
|
|
u32 node_index)
|
|
|
|
|
{
|
|
|
|
|
rdma_main_t *rm = &rdma_main;
|
|
|
|
|
vnet_hw_interface_t *hw = vnet_get_hw_interface (vnm, hw_if_index);
|
|
|
|
|
rdma_device_t *rd = pool_elt_at_index (rm->devices, hw->dev_instance);
|
|
|
|
|
rd->per_interface_next_index =
|
2019-11-05 17:46:17 +01:00
|
|
|
~0 ==
|
|
|
|
|
node_index ? VNET_DEVICE_INPUT_NEXT_ETHERNET_INPUT :
|
2019-03-25 11:41:34 +01:00
|
|
|
vlib_node_add_next (vlib_get_main (), rdma_input_node.index, node_index);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static char *rdma_tx_func_error_strings[] = {
|
|
|
|
|
#define _(n,s) s,
|
|
|
|
|
foreach_rdma_tx_func_error
|
|
|
|
|
#undef _
|
|
|
|
|
};
|
|
|
|
|
|
2019-08-12 11:44:20 +02:00
|
|
|
VNET_DEVICE_CLASS (rdma_device_class) =
|
2019-03-25 11:41:34 +01:00
|
|
|
{
|
|
|
|
|
.name = "RDMA interface",
|
|
|
|
|
.format_device = format_rdma_device,
|
|
|
|
|
.format_device_name = format_rdma_device_name,
|
|
|
|
|
.admin_up_down_function = rdma_interface_admin_up_down,
|
|
|
|
|
.rx_redirect_to_node = rdma_set_interface_next_node,
|
|
|
|
|
.tx_function_n_errors = RDMA_TX_N_ERROR,
|
|
|
|
|
.tx_function_error_strings = rdma_tx_func_error_strings,
|
2019-08-12 11:44:20 +02:00
|
|
|
.mac_addr_change_function = rdma_mac_change,
|
2019-03-25 11:41:34 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
clib_error_t *
|
|
|
|
|
rdma_init (vlib_main_t * vm)
|
|
|
|
|
{
|
|
|
|
|
rdma_main_t *rm = &rdma_main;
|
2020-03-02 17:36:30 +01:00
|
|
|
vlib_thread_main_t *tm = vlib_get_thread_main ();
|
2019-03-25 11:41:34 +01:00
|
|
|
|
|
|
|
|
rm->log_class = vlib_log_register_class ("rdma", 0);
|
|
|
|
|
|
2020-03-02 17:36:30 +01:00
|
|
|
/* vlib_buffer_t template */
|
|
|
|
|
vec_validate_aligned (rm->per_thread_data, tm->n_vlib_mains - 1,
|
|
|
|
|
CLIB_CACHE_LINE_BYTES);
|
|
|
|
|
|
|
|
|
|
for (int i = 0; i < tm->n_vlib_mains; i++)
|
|
|
|
|
{
|
|
|
|
|
rdma_per_thread_data_t *ptd = vec_elt_at_index (rm->per_thread_data, i);
|
|
|
|
|
clib_memset (&ptd->buffer_template, 0, sizeof (vlib_buffer_t));
|
|
|
|
|
ptd->buffer_template.flags = VLIB_BUFFER_TOTAL_LENGTH_VALID;
|
|
|
|
|
ptd->buffer_template.ref_count = 1;
|
|
|
|
|
vnet_buffer (&ptd->buffer_template)->sw_if_index[VLIB_TX] = (u32) ~ 0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-03-25 11:41:34 +01:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2023-07-28 13:19:49 +02:00
|
|
|
VLIB_INIT_FUNCTION (rdma_init);
|