737edea328
Add a new native idpf driver. This patch enables the device initialization. Add some necessary functions and definations for input and output. A new version of virtchnl is introduced. Type: feature Signed-off-by: Ting Xu <ting.xu@intel.com> Change-Id: Ibbd9cd645e64469f1c4c8b33346c1301be3f6927
611 lines
21 KiB
C
611 lines
21 KiB
C
/*
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*------------------------------------------------------------------
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* Copyright (c) 2023 Intel and/or its affiliates.
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*------------------------------------------------------------------
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*/
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#ifndef _IDPF_VIRTCHNL_LAN_DESC_H_
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#define _IDPF_VIRTCHNL_LAN_DESC_H_
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/* VIRTCHNL2_TX_DESC_IDS
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* Transmit descriptor ID flags
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*/
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#define foreach_idpf_txdid \
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_ (0, DATA) \
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_ (1, CTX) \
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_ (2, REINJECT_CTX) \
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_ (3, FLEX_DATA) \
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_ (4, FLEX_CTX) \
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_ (5, FLEX_TSO_CTX) \
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_ (6, FLEX_TSYN_L2TAG1) \
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_ (7, FLEX_L2TAG1_L2TAG2) \
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_ (8, FLEX_TSO_L2TAG2_PARSTAG_CTX) \
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_ (9, FLEX_HOSTSPLIT_SA_TSO_CTX) \
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_ (10, FLEX_HOSTSPLIT_SA_CTX) \
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_ (11, FLEX_L2TAG2_CTX) \
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_ (12, FLEX_FLOW_SCHED) \
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_ (13, FLEX_HOSTSPLIT_TSO_CTX) \
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_ (14, FLEX_HOSTSPLIT_CTX) \
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_ (15, DESC_DONE)
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typedef enum
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{
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#define _(a, b) VIRTCHNL2_TXDID_##b = (1 << a),
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foreach_idpf_txdid
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#undef _
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} idpf_txdid_t;
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/* VIRTCHNL2_RX_DESC_IDS
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* Receive descriptor IDs (range from 0 to 63)
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*/
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#define foreach_virtchnl2_rxdid \
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_ (0, 0_16B_BASE) \
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_ (1, 1_32B_BASE) \
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_ (2, 2_FLEX_SPLITQ) \
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_ (2, 2_FLEX_SQ_NIC) \
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_ (3, 3_FLEX_SQ_SW) \
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_ (4, 4_FLEX_SQ_NIC_VEB) \
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_ (5, 5_FLEX_SQ_NIC_ACL) \
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_ (6, 6_FLEX_SQ_NIC_2) \
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_ (7, 7_HW_RSVD) \
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_ (16, 16_COMMS_GENERIC) \
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_ (17, 17_COMMS_AUX_VLAN) \
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_ (18, 18_COMMS_AUX_IPV4) \
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_ (19, 19_COMMS_AUX_IPV6) \
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_ (20, 20_COMMS_AUX_FLOW) \
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_ (21, 21_COMMS_AUX_TCP)
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typedef enum
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{
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#define _(v, n) VIRTCHNL2_RXDID_##n = v,
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foreach_virtchnl2_rxdid
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#undef _
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} virtchnl2_rxdid_t;
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/* VIRTCHNL2_RX_DESC_ID_BITMASKS
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* Receive descriptor ID bitmasks
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*/
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#define VIRTCHNL2_RXDID_0_16B_BASE_M BIT (VIRTCHNL2_RXDID_0_16B_BASE)
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#define VIRTCHNL2_RXDID_1_32B_BASE_M BIT (VIRTCHNL2_RXDID_1_32B_BASE)
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#define VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M BIT (VIRTCHNL2_RXDID_2_FLEX_SPLITQ)
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#define VIRTCHNL2_RXDID_2_FLEX_SQ_NIC_M BIT (VIRTCHNL2_RXDID_2_FLEX_SQ_NIC)
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#define VIRTCHNL2_RXDID_3_FLEX_SQ_SW_M BIT (VIRTCHNL2_RXDID_3_FLEX_SQ_SW)
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#define VIRTCHNL2_RXDID_4_FLEX_SQ_NIC_VEB_M \
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BIT (VIRTCHNL2_RXDID_4_FLEX_SQ_NIC_VEB)
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#define VIRTCHNL2_RXDID_5_FLEX_SQ_NIC_ACL_M \
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BIT (VIRTCHNL2_RXDID_5_FLEX_SQ_NIC_ACL)
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#define VIRTCHNL2_RXDID_6_FLEX_SQ_NIC_2_M BIT (VIRTCHNL2_RXDID_6_FLEX_SQ_NIC_2)
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#define VIRTCHNL2_RXDID_7_HW_RSVD_M BIT (VIRTCHNL2_RXDID_7_HW_RSVD)
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/* 9 through 15 are reserved */
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#define VIRTCHNL2_RXDID_16_COMMS_GENERIC_M \
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BIT (VIRTCHNL2_RXDID_16_COMMS_GENERIC)
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#define VIRTCHNL2_RXDID_17_COMMS_AUX_VLAN_M \
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BIT (VIRTCHNL2_RXDID_17_COMMS_AUX_VLAN)
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#define VIRTCHNL2_RXDID_18_COMMS_AUX_IPV4_M \
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BIT (VIRTCHNL2_RXDID_18_COMMS_AUX_IPV4)
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#define VIRTCHNL2_RXDID_19_COMMS_AUX_IPV6_M \
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BIT (VIRTCHNL2_RXDID_19_COMMS_AUX_IPV6)
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#define VIRTCHNL2_RXDID_20_COMMS_AUX_FLOW_M \
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BIT (VIRTCHNL2_RXDID_20_COMMS_AUX_FLOW)
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#define VIRTCHNL2_RXDID_21_COMMS_AUX_TCP_M \
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BIT (VIRTCHNL2_RXDID_21_COMMS_AUX_TCP)
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/* 22 through 63 are reserved */
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/* Rx */
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/* For splitq virtchnl2_rx_flex_desc_adv desc members */
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S 0
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_M \
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MAKEMASK (0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S)
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S 0
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_M \
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MAKEMASK (0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S)
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S 10
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_M \
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MAKEMASK (0x3UL, VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S)
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S 12
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_M \
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MAKEMASK (0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S)
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S 0
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M \
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MAKEMASK (0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S)
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S 14
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_M \
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BIT_ULL (VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S)
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_S 15
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_M \
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BIT_ULL (VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_S)
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S 0
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_M \
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MAKEMASK (0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S)
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S 10
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_M \
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BIT_ULL (VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S)
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_S 11
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_M \
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BIT_ULL (VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_S)
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S 12
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_M \
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BIT_ULL (VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S)
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_S 13
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#define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M \
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MAKEMASK (0x7UL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M)
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#define foreach_virtchnl2_rx_flex_desc_adv_status0_qw1 \
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_ (0, DD_S) \
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_ (1, EOF_S) \
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_ (2, HBO_S) \
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_ (3, L3L4P_S) \
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_ (4, XSUM_IPE_S) \
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_ (5, XSUM_L4E_S) \
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_ (6, XSUM_EIPE_S) \
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_ (7, XSUM_EUDPE_S)
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typedef enum
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{
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#define _(v, n) VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_##n = v,
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foreach_virtchnl2_rx_flex_desc_adv_status0_qw1
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#undef _
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} virtchnl2_rx_flex_desc_adv_status0_qw1_t;
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#define foreach_virtchnl2_rx_flex_desc_adv_status0_qw0 \
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_ (0, LPBK_S) \
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_ (1, IPV6EXADD_S) \
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_ (2, RXE_S) \
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_ (3, CRCP_S) \
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_ (4, RSS_VALID_S) \
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_ (5, L2TAG1P_S) \
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_ (6, XTRMD0_VALID_S) \
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_ (7, XTRMD1_VALID_S) \
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_ (8, LAST)
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typedef enum
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{
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#define _(v, n) VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_##n = v,
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foreach_virtchnl2_rx_flex_desc_adv_status0_qw0
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#undef _
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} virtchnl2_rx_flex_desc_adv_status0_qw0_t;
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#define foreach_virtchnl2_rx_flex_desc_adv_status1 \
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_ (0, RSVD_S) \
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_ (2, ATRAEFAIL_S) \
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_ (3, L2TAG2P_S) \
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_ (4, XTRMD2_VALID_S) \
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_ (5, XTRMD3_VALID_S) \
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_ (6, XTRMD4_VALID_S) \
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_ (7, XTRMD5_VALID_S) \
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_ (8, LAST)
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typedef enum
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{
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#define _(v, n) VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_##n = v,
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foreach_virtchnl2_rx_flex_desc_adv_status1
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#undef _
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} virtchnl2_rx_flex_desc_adv_status1_t;
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#define VIRTCHNL2_RX_FLEX_DESC_PTYPE_S 0
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#define VIRTCHNL2_RX_FLEX_DESC_PTYPE_M \
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MAKEMASK (0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_PTYPE_S) /* 10 bits */
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#define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S 0
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#define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_M \
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MAKEMASK (0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S) /* 14 bits */
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#define foreach_virtchnl2_rx_flex_desc_status0 \
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_ (0, DD_S) \
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_ (1, EOF_S) \
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_ (2, HBO_S) \
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_ (3, L3L4P_S) \
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_ (4, XSUM_IPE_S) \
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_ (5, XSUM_L4E_S) \
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_ (6, XSUM_EIPE_S) \
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_ (7, XSUM_EUDPE_S) \
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_ (8, LPBK_S) \
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_ (9, IPV6EXADD_S) \
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_ (10, RXE_S) \
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_ (11, CRCP_S) \
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_ (12, RSS_VALID_S) \
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_ (13, L2TAG1P_S) \
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_ (14, XTRMD0_VALID_S) \
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_ (15, XTRMD1_VALID_S) \
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_ (16, LAST)
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typedef enum
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{
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#define _(v, n) VIRTCHNL2_RX_FLEX_DESC_STATUS0_##n = v,
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foreach_virtchnl2_rx_flex_desc_status0
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#undef _
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} virtchnl2_rx_flex_desc_status0_t;
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#define foreach_virtchnl2_rx_flex_desc_status1 \
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_ (0, CPM_S) \
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_ (4, NAT_S) \
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_ (5, CRYPTO_S) \
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_ (11, L2TAG2P_S) \
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_ (12, XTRMD2_VALID_S) \
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_ (13, XTRMD3_VALID_S) \
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_ (14, XTRMD4_VALID_S) \
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_ (15, XTRMD5_VALID_S) \
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_ (16, LAST)
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typedef enum
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{
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#define _(v, n) VIRTCHNL2_RX_FLEX_DESC_STATUS1_##n = v,
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foreach_virtchnl2_rx_flex_desc_status1
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#undef _
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} virtchnl2_rx_flex_desc_status1_t;
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#define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_SPH_S 63
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#define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_SPH_M \
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BIT_ULL (VIRTCHNL2_RX_BASE_DESC_QW1_LEN_SPH_S)
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#define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S 52
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#define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_M \
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MAKEMASK (0x7FFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S)
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#define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S 38
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#define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_M \
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MAKEMASK (0x3FFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S)
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#define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S 30
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#define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_M \
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MAKEMASK (0xFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S)
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#define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S 19
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#define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_M \
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MAKEMASK (0xFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S)
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#define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S 0
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#define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_M \
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MAKEMASK (0x7FFFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S)
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#define foreach_virtchnl2_rx_base_desc_status \
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_ (0, DD_S) \
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_ (1, EOF_S) \
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_ (2, L2TAG1P_S) \
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_ (3, L3L4P_S) \
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_ (4, CRCP_S) \
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_ (5, RSVD_S) \
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_ (8, EXT_UDP_0_S) \
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_ (9, UMBCAST_S) \
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_ (11, FLM_S) \
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_ (12, FLTSTAT_S) \
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_ (14, LPBK_S) \
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_ (15, IPV6EXADD_S) \
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_ (16, RSVD1_S) \
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_ (18, INT_UDP_0_S) \
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_ (19, LAST)
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typedef enum
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{
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#define _(v, n) VIRTCHNL2_RX_BASE_DESC_STATUS_##n = v,
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foreach_virtchnl2_rx_base_desc_status
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#undef _
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} virtchnl2_rx_base_desc_status_t;
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#define VIRTCHNL2_RX_BASE_DESC_EXT_STATUS_L2TAG2P_S 0
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#define foreach_virtchnl2_rx_base_desc_error \
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_ (0, RXE_S) \
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_ (1, ATRAEFAIL_S) \
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_ (2, HBO_S) \
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_ (3, L3L4E_S) \
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_ (3, IPE_S) \
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_ (4, L4E_S) \
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_ (5, EIPE_S) \
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_ (6, OVERSIZE_S) \
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_ (7, PPRS_S)
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typedef enum
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{
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#define _(v, n) VIRTCHNL2_RX_BASE_DESC_ERROR_##n = v,
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foreach_virtchnl2_rx_base_desc_error
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#undef _
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} virtchnl2_rx_base_desc_error_t;
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#define foreach_virtchnl2_rx_base_desc_fltstat \
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_ (0, NO_DATA) \
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_ (1, FD_ID) \
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_ (2, RSV) \
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_ (3, RSS_HASH)
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typedef enum
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{
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#define _(v, n) VIRTCHNL2_RX_BASE_DESC_FLTSTAT_##n = v,
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foreach_virtchnl2_rx_base_desc_fltstat
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#undef _
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} virtchnl2_rx_base_desc_fltstat_t;
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/* Receive Descriptors */
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/* splitq buf
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| 16| 0|
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----------------------------------------------------------------
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| RSV | Buffer ID |
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----------------------------------------------------------------
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| Rx packet buffer adresss |
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----------------------------------------------------------------
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| Rx header buffer adresss |
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----------------------------------------------------------------
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| RSV |
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----------------------------------------------------------------
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| 0|
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*/
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typedef struct
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{
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struct
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{
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u16 buf_id;
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u16 rsvd0;
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u32 rsvd1;
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} qword0;
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u64 pkt_addr;
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u64 hdr_addr;
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u64 rsvd2;
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} virtchnl2_splitq_rx_buf_desc_t;
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typedef struct
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{
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u64 pkt_addr;
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u64 hdr_addr;
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u64 rsvd1;
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u64 rsvd2;
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} virtchnl2_singleq_rx_buf_desc_t;
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union virtchnl2_rx_buf_desc
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{
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virtchnl2_singleq_rx_buf_desc_t read;
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virtchnl2_splitq_rx_buf_desc_t split_rd;
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};
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typedef struct
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{
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struct
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{
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struct
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{
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u16 mirroring_status;
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u16 l2tag1;
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} lo_dword;
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union
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{
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u32 rss;
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u32 fd_id;
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} hi_dword;
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} qword0;
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struct
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{
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u64 status_error_ptype_len;
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} qword1;
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struct
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{
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u16 ext_status;
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u16 rsvd;
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u16 l2tag2_1;
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u16 l2tag2_2;
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} qword2;
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struct
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{
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u32 reserved;
|
|
u32 fd_id;
|
|
} qword3;
|
|
} virtchnl2_singleq_base_rx_desc_t;
|
|
|
|
typedef struct
|
|
{
|
|
/* Qword 0 */
|
|
u8 rxdid;
|
|
u8 mir_id_umb_cast;
|
|
u16 ptype_flex_flags0;
|
|
u16 pkt_len;
|
|
u16 hdr_len_sph_flex_flags1;
|
|
|
|
/* Qword 1 */
|
|
u16 status_error0;
|
|
u16 l2tag1;
|
|
u16 flex_meta0;
|
|
u16 flex_meta1;
|
|
|
|
/* Qword 2 */
|
|
u16 status_error1;
|
|
u8 flex_flags2;
|
|
u8 time_stamp_low;
|
|
u16 l2tag2_1st;
|
|
u16 l2tag2_2nd;
|
|
|
|
/* Qword 3 */
|
|
u16 flex_meta2;
|
|
u16 flex_meta3;
|
|
union
|
|
{
|
|
struct
|
|
{
|
|
u16 flex_meta4;
|
|
u16 flex_meta5;
|
|
} flex;
|
|
u32 ts_high;
|
|
} flex_ts;
|
|
} virtchnl2_rx_flex_desc_t;
|
|
|
|
typedef struct
|
|
{
|
|
/* Qword 0 */
|
|
u8 rxdid;
|
|
u8 mir_id_umb_cast;
|
|
u16 ptype_flex_flags0;
|
|
u16 pkt_len;
|
|
u16 hdr_len_sph_flex_flags1;
|
|
|
|
/* Qword 1 */
|
|
u16 status_error0;
|
|
u16 l2tag1;
|
|
u32 rss_hash;
|
|
|
|
/* Qword 2 */
|
|
u16 status_error1;
|
|
u8 flexi_flags2;
|
|
u8 ts_low;
|
|
u16 l2tag2_1st;
|
|
u16 l2tag2_2nd;
|
|
|
|
/* Qword 3 */
|
|
u32 flow_id;
|
|
union
|
|
{
|
|
struct
|
|
{
|
|
u16 rsvd;
|
|
u16 flow_id_ipv6;
|
|
} flex;
|
|
u32 ts_high;
|
|
} flex_ts;
|
|
} virtchnl2_rx_flex_desc_nic_t;
|
|
|
|
typedef struct
|
|
{
|
|
/* Qword 0 */
|
|
u8 rxdid;
|
|
u8 mir_id_umb_cast;
|
|
u16 ptype_flex_flags0;
|
|
u16 pkt_len;
|
|
u16 hdr_len_sph_flex_flags1;
|
|
|
|
/* Qword 1 */
|
|
u16 status_error0;
|
|
u16 l2tag1;
|
|
u16 src_vsi;
|
|
u16 flex_md1_rsvd;
|
|
|
|
/* Qword 2 */
|
|
u16 status_error1;
|
|
u8 flex_flags2;
|
|
u8 ts_low;
|
|
u16 l2tag2_1st;
|
|
u16 l2tag2_2nd;
|
|
|
|
/* Qword 3 */
|
|
u32 rsvd;
|
|
u32 ts_high;
|
|
} virtchnl2_rx_flex_desc_sw_t;
|
|
|
|
typedef struct
|
|
{
|
|
/* Qword 0 */
|
|
u8 rxdid;
|
|
u8 mir_id_umb_cast;
|
|
u16 ptype_flex_flags0;
|
|
u16 pkt_len;
|
|
u16 hdr_len_sph_flex_flags1;
|
|
|
|
/* Qword 1 */
|
|
u16 status_error0;
|
|
u16 l2tag1;
|
|
u32 rss_hash;
|
|
|
|
/* Qword 2 */
|
|
u16 status_error1;
|
|
u8 flexi_flags2;
|
|
u8 ts_low;
|
|
u16 l2tag2_1st;
|
|
u16 l2tag2_2nd;
|
|
|
|
/* Qword 3 */
|
|
u16 flow_id;
|
|
u16 src_vsi;
|
|
union
|
|
{
|
|
struct
|
|
{
|
|
u16 rsvd;
|
|
u16 flow_id_ipv6;
|
|
} flex;
|
|
u32 ts_high;
|
|
} flex_ts;
|
|
} virtchnl2_rx_flex_desc_nic_2_t;
|
|
|
|
typedef struct
|
|
{
|
|
/* Qword 0 */
|
|
u8 rxdid_ucast;
|
|
u8 status_err0_qw0;
|
|
u16 ptype_err_fflags0;
|
|
u16 pktlen_gen_bufq_id;
|
|
u16 hdrlen_flags;
|
|
|
|
/* Qword 1 */
|
|
u8 status_err0_qw1;
|
|
u8 status_err1;
|
|
u8 fflags1;
|
|
u8 ts_low;
|
|
u16 fmd0;
|
|
u16 fmd1;
|
|
/* Qword 2 */
|
|
u16 fmd2;
|
|
u8 fflags2;
|
|
u8 hash3;
|
|
u16 fmd3;
|
|
u16 fmd4;
|
|
/* Qword 3 */
|
|
u16 fmd5;
|
|
u16 fmd6;
|
|
u16 fmd7_0;
|
|
u16 fmd7_1;
|
|
} virtchnl2_rx_flex_desc_adv_t;
|
|
|
|
typedef struct
|
|
{
|
|
/* Qword 0 */
|
|
u8 rxdid_ucast;
|
|
u8 status_err0_qw0;
|
|
u16 ptype_err_fflags0;
|
|
u16 pktlen_gen_bufq_id;
|
|
u16 hdrlen_flags;
|
|
|
|
/* Qword 1 */
|
|
u8 status_err0_qw1;
|
|
u8 status_err1;
|
|
u8 fflags1;
|
|
u8 ts_low;
|
|
u16 buf_id;
|
|
union
|
|
{
|
|
u16 raw_cs;
|
|
u16 l2tag1;
|
|
u16 rscseglen;
|
|
} misc;
|
|
/* Qword 2 */
|
|
u16 hash1;
|
|
union
|
|
{
|
|
u8 fflags2;
|
|
u8 mirrorid;
|
|
u8 hash2;
|
|
} ff2_mirrid_hash2;
|
|
u8 hash3;
|
|
u16 l2tag2;
|
|
u16 fmd4;
|
|
/* Qword 3 */
|
|
u16 l2tag1;
|
|
u16 fmd6;
|
|
u32 ts_high;
|
|
} virtchnl2_rx_flex_desc_adv_nic_3_t;
|
|
|
|
typedef union
|
|
{
|
|
virtchnl2_singleq_rx_buf_desc_t read;
|
|
virtchnl2_singleq_base_rx_desc_t base_wb;
|
|
virtchnl2_rx_flex_desc_t flex_wb;
|
|
virtchnl2_rx_flex_desc_nic_t flex_nic_wb;
|
|
virtchnl2_rx_flex_desc_sw_t flex_sw_wb;
|
|
virtchnl2_rx_flex_desc_nic_2_t flex_nic_2_wb;
|
|
virtchnl2_rx_flex_desc_adv_t flex_adv_wb;
|
|
virtchnl2_rx_flex_desc_adv_nic_3_t flex_adv_nic_3_wb;
|
|
u64 qword[4];
|
|
} virtchnl2_rx_desc_t;
|
|
|
|
#endif /* _IDPF_VIRTCHNL_LAN_DESC_H_ */
|