2d725c6128
Type: feature Change-Id: Icd9de05f2cbac0e5a6dfb1f1414f21dc4b893104 Signed-off-by: Damjan Marion <damarion@cisco.com>
686 lines
16 KiB
C
686 lines
16 KiB
C
/* SPDX-License-Identifier: Apache-2.0
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* Copyright(c) 2023 Cisco Systems, Inc.
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*/
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#ifndef _ENA_ADMIN_DEFS_H_
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#define _ENA_ADMIN_DEFS_H_
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#include <vppinfra/clib.h>
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#include <vppinfra/error_bootstrap.h>
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#define foreach_ena_aq_opcode \
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_ (1, CREATE_SQ) \
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_ (2, DESTROY_SQ) \
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_ (3, CREATE_CQ) \
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_ (4, DESTROY_CQ) \
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_ (8, GET_FEATURE) \
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_ (9, SET_FEATURE) \
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_ (11, GET_STATS)
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typedef enum
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{
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#define _(v, n) ENA_AQ_OPCODE_##n = (v),
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foreach_ena_aq_opcode
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#undef _
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} __clib_packed ena_aq_opcode_t;
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#define foreach_ena_aq_compl_status \
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_ (0, SUCCESS) \
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_ (1, RESOURCE_ALLOCATION_FAILURE) \
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_ (2, BAD_OPCODE) \
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_ (3, UNSUPPORTED_OPCODE) \
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_ (4, MALFORMED_REQUEST) \
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_ (5, ILLEGAL_PARAMETER) \
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_ (6, UNKNOWN_ERROR) \
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_ (7, RESOURCE_BUSY)
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typedef enum
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{
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#define _(v, n) ENA_ADMIN_COMPL_STATUS_##n = (v),
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foreach_ena_aq_compl_status
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#undef _
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} __clib_packed ena_aq_compl_status_t;
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/* id, versiom, get, set, name, struct */
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#define foreach_ena_aq_feature_id \
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_ (1, 0, 1, 0, DEVICE_ATTRIBUTES, ena_aq_feat_device_attr_t) \
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_ (2, 0, 1, 0, MAX_QUEUES_NUM, ena_aq_feat_max_queue_num_t) \
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_ (3, 0, 1, 0, HW_HINTS, ena_aq_feat_hw_hints_t) \
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_ (4, 0, 1, 1, LLQ, ena_aq_feat_llq_t) \
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_ (5, 0, 1, 0, EXTRA_PROPERTIES_STRINGS, \
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ena_aq_feat_extra_properties_strings_t) \
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_ (6, 0, 1, 0, EXTRA_PROPERTIES_FLAGS, \
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ena_aq_feat_extra_properties_flags_t) \
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_ (7, 1, 1, 0, MAX_QUEUES_EXT, ena_aq_feat_max_queue_ext_t) \
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_ (10, 0, 1, 1, RSS_HASH_FUNCTION, ena_aq_feat_rss_hash_function_t) \
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_ (11, 0, 1, 0, STATELESS_OFFLOAD_CONFIG, \
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ena_aq_feat_stateless_offload_config_t) \
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_ (12, 0, 1, 1, RSS_INDIRECTION_TABLE_CONFIG, \
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ena_aq_feat_rss_ind_table_config_t) \
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_ (14, 0, 0, 1, MTU, ena_aq_feat_mtu_t) \
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_ (18, 0, 1, 1, RSS_HASH_INPUT, ena_aq_feat_rss_hash_input_t) \
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_ (20, 0, 1, 0, INTERRUPT_MODERATION, ena_aq_feat_intr_moder_t) \
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_ (26, 0, 1, 1, AENQ_CONFIG, ena_aq_feat_aenq_config_t) \
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_ (27, 0, 1, 0, LINK_CONFIG, ena_aq_feat_link_config_t) \
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_ (28, 0, 0, 1, HOST_ATTR_CONFIG, ena_aq_feat_host_attr_config_t) \
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_ (29, 0, 1, 1, PHC_CONFIG, ena_aq_feat_phc_config_t)
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typedef enum
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{
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#define _(v, ver, r, w, n, s) ENA_ADMIN_FEAT_ID_##n = (v),
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foreach_ena_aq_feature_id
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#undef _
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} __clib_packed ena_aq_feature_id_t;
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#define foreach_ena_aq_stats_type \
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_ (0, BASIC) \
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_ (1, EXTENDED) \
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_ (2, ENI)
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#define foreach_ena_aq_stats_scope \
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_ (0, SPECIFIC_QUEUE) \
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_ (1, ETH_TRAFFIC)
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typedef enum
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{
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#define _(v, n) ENA_ADMIN_STATS_TYPE_##n = (v),
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foreach_ena_aq_stats_type
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#undef _
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} __clib_packed ena_aq_stats_type_t;
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typedef enum
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{
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#define _(v, n) ENA_ADMIN_STATS_SCOPE_##n = (v),
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foreach_ena_aq_stats_scope
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#undef _
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} __clib_packed ena_aq_stats_scope_t;
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typedef struct
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{
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u32 addr_lo;
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u16 addr_hi;
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u16 _reserved_16;
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} ena_mem_addr_t;
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#define foreach_ena_aq_aenq_groups \
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_ (link_change) \
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_ (fatal_error) \
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_ (warning) \
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_ (notification) \
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_ (keep_alive) \
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_ (refresh_capabilities) \
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_ (conf_notifications)
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typedef union
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{
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struct
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{
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#define _(g) u32 g : 1;
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foreach_ena_aq_aenq_groups
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#undef _
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};
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u32 as_u32;
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} ena_aq_aenq_groups_t;
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STATIC_ASSERT_SIZEOF (ena_aq_aenq_groups_t, 4);
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typedef struct
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{
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u32 length;
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ena_mem_addr_t addr;
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} ena_aq_aq_ctrl_buff_info_t;
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typedef struct
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{
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u32 impl_id;
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u32 device_version;
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u32 supported_features;
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u32 _reserved3;
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u32 phys_addr_width;
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u32 virt_addr_width;
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u8 mac_addr[6];
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u8 _reserved7[2];
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u32 max_mtu;
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} ena_aq_feat_device_attr_t;
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typedef struct
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{
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union
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{
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struct
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{
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u16 l3_sort : 1;
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u16 l4_sort : 1;
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};
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u16 supported_input_sort;
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};
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union
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{
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struct
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{
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u16 enable_l3_sort : 1;
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u16 enable_l4_sort : 1;
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};
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u16 enabled_input_sort;
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};
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} ena_aq_feat_rss_hash_input_t;
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STATIC_ASSERT_SIZEOF (ena_aq_feat_rss_hash_input_t, 4);
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typedef struct
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{
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u16 intr_delay_resolution;
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u16 reserved;
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} ena_aq_feat_intr_moder_t;
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typedef struct
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{
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ena_aq_aenq_groups_t supported_groups;
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ena_aq_aenq_groups_t enabled_groups;
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} ena_aq_feat_aenq_config_t;
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#define foreach_ena_aq_link_types \
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_ (0, 1000, 1G) \
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_ (1, 2500, 2_5G) \
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_ (2, 5000, 5G) \
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_ (3, 10000, 10G) \
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_ (4, 25000, 25G) \
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_ (5, 40000, 40G) \
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_ (6, 50000, 50G) \
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_ (7, 100000, 100G) \
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_ (8, 200000, 200G) \
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_ (9, 400000, 400G)
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typedef enum
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{
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#define _(b, v, n) ENA_ADMIN_LINK_TYPE_##n = (1U << b),
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foreach_ena_aq_link_types
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#undef _
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} ena_aq_link_types_t;
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typedef struct
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{
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u32 speed;
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ena_aq_link_types_t supported;
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u32 autoneg : 1;
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u32 duplex : 1;
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} ena_aq_feat_link_config_t;
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STATIC_ASSERT_SIZEOF (ena_aq_feat_link_config_t, 12);
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typedef struct
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{
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u32 tx;
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u32 rx_supported;
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u32 rx_enabled;
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} ena_aq_feat_stateless_offload_config_t;
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typedef struct
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{
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u16 cq_idx;
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u16 reserved;
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} ena_aq_feat_rss_ind_table_entry_t;
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typedef struct
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{
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u16 min_size;
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u16 max_size;
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u16 size;
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u8 one_entry_update : 1;
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u8 reserved;
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u32 inline_index;
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ena_aq_feat_rss_ind_table_entry_t inline_entry;
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} ena_aq_feat_rss_ind_table_config_t;
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typedef struct
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{
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u32 mtu;
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} ena_aq_feat_mtu_t;
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typedef struct
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{
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u32 count;
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} ena_aq_feat_extra_properties_strings_t;
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typedef struct
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{
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u32 flags;
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} ena_aq_feat_extra_properties_flags_t;
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typedef struct
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{
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u32 max_sq_num;
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u32 max_sq_depth;
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u32 max_cq_num;
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u32 max_cq_depth;
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u32 max_legacy_llq_num;
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u32 max_legacy_llq_depth;
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u32 max_header_size;
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u16 max_packet_tx_descs;
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u16 max_packet_rx_descs;
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} ena_aq_feat_max_queue_num_t;
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typedef struct
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{
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u16 mmio_read_timeout;
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u16 driver_watchdog_timeout;
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u16 missing_tx_completion_timeout;
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u16 missed_tx_completion_count_threshold_to_reset;
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u16 admin_completion_tx_timeout;
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u16 netdev_wd_timeout;
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u16 max_tx_sgl_size;
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u16 max_rx_sgl_size;
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u16 reserved[8];
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} ena_aq_feat_hw_hints_t;
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typedef struct
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{
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u8 version;
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u8 _reserved1[3];
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u32 max_tx_sq_num;
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u32 max_tx_cq_num;
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u32 max_rx_sq_num;
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u32 max_rx_cq_num;
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u32 max_tx_sq_depth;
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u32 max_tx_cq_depth;
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u32 max_rx_sq_depth;
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u32 max_rx_cq_depth;
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u32 max_tx_header_size;
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u16 max_per_packet_tx_descs;
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u16 max_per_packet_rx_descs;
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} ena_aq_feat_max_queue_ext_t;
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typedef struct
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{
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u32 supported_func;
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u32 selected_func;
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u32 init_val;
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} ena_aq_feat_rss_hash_function_t;
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typedef struct
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{
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ena_mem_addr_t os_info_ba;
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ena_mem_addr_t debug_ba;
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u32 debug_area_size;
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} ena_aq_feat_host_attr_config_t;
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typedef struct
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{
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u8 type;
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u8 reserved1[3];
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u32 doorbell_offset;
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u32 expire_timeout_usec;
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u32 block_timeout_usec;
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ena_mem_addr_t output_address;
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u32 output_length;
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} ena_aq_feat_phc_config_t;
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typedef struct
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{
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u32 max_llq_num;
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u32 max_llq_depth;
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u16 header_location_ctrl_supported;
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u16 header_location_ctrl_enabled;
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u16 entry_size_ctrl_supported;
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u16 entry_size_ctrl_enabled;
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u16 desc_num_before_header_supported;
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u16 desc_num_before_header_enabled;
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u16 descriptors_stride_ctrl_supported;
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u16 descriptors_stride_ctrl_enabled;
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union
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{
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struct
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{
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u16 supported_flags;
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u16 max_tx_burst_size;
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} get;
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struct
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{
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u16 enabled_flags;
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} set;
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} accel_mode;
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} ena_aq_feat_llq_t;
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typedef struct
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{
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/* feat common */
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u8 flags;
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ena_aq_feature_id_t feature_id;
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u8 feature_version;
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u8 _reserved;
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} ena_aq_get_set_feature_common_desc_t;
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STATIC_ASSERT_SIZEOF (ena_aq_get_set_feature_common_desc_t, 4);
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typedef struct
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{
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ena_aq_aq_ctrl_buff_info_t control_buffer;
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ena_aq_stats_type_t type;
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ena_aq_stats_scope_t scope;
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u16 _reserved3;
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u16 queue_idx;
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u16 device_id;
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} ena_aq_get_stats_cmd_t;
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STATIC_ASSERT_SIZEOF (ena_aq_get_stats_cmd_t, 20);
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typedef enum
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{
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ENA_ADMIN_SQ_DIRECTION_TX = 1,
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ENA_ADMIN_SQ_DIRECTION_RX = 2,
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} ena_aq_sq_direction_t;
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typedef enum
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{
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ENA_ADMIN_SQ_PLACEMENT_POLICY_HOST = 1,
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ENA_ADMIN_SQ_PLACEMENT_POLICY_DEVICE = 3,
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} ena_aq_sq_placement_policy_t;
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typedef enum
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{
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ENA_ADMIN_SQ_COMPLETION_POLICY_DESC = 0,
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ENA_ADMIN_SQ_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
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ENA_ADMIN_SQ_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
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ENA_ADMIN_SQ_COMPLETION_POLICY_HEAD = 3,
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} ena_aq_completion_policy_t;
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typedef struct
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{
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union
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{
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struct
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{
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u8 _reserved0_0 : 5;
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u8 sq_direction : 3; /* ena_aq_sq_direction_t */
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};
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u8 sq_identity;
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};
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u8 _reserved1;
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union
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{
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struct
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{
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u8 placement_policy : 4; /* ena_aq_sq_placement_policy_t */
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u8 completion_policy : 3; /* ena_aq_completion_policy_t */
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u8 _reserved2_7 : 1;
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};
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u8 sq_caps_2;
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};
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union
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{
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struct
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{
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u8 is_physically_contiguous : 1;
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u8 _reserved3_1 : 7;
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};
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u8 sq_caps_3;
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};
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u16 cq_idx;
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u16 sq_depth;
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ena_mem_addr_t sq_ba;
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ena_mem_addr_t sq_head_writeback; /* used if completion_policy is 2 or 3 */
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u32 _reserved0_w7;
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u32 _reserved0_w8;
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} ena_aq_create_sq_cmd_t;
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typedef struct
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{
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u16 sq_idx;
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u16 _reserved;
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u32 sq_doorbell_offset; /* REG BAR offset of queue dorbell */
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u32 llq_descriptors_offset; /* LLQ MEM BAR offset of descriptors */
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u32 llq_headers_offset; /* LLQ MEM BAR offset of headers mem */
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} ena_aq_create_sq_resp_t;
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typedef struct
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{
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union
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{
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struct
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{
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u8 _reserved0_0 : 5;
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u8 interrupt_mode_enabled : 1;
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u8 _reserved0_6 : 2;
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};
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u8 cq_caps_1;
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};
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union
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{
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struct
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{
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u8 cq_entry_size_words : 4;
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u8 _reserved1_4 : 4;
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};
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u8 cq_caps_2;
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};
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u16 cq_depth;
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u32 msix_vector;
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ena_mem_addr_t cq_ba;
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} ena_aq_create_cq_cmd_t;
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typedef struct
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{
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u16 cq_idx;
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u16 cq_actual_depth;
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u32 numa_node_register_offset;
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u32 cq_head_db_register_offset;
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u32 cq_interrupt_unmask_register_offset;
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} ena_aq_create_cq_resp_t;
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typedef struct
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{
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u16 sq_idx;
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union
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{
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struct
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{
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u8 _reserved : 5;
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u8 sq_direction : 3; /* ena_aq_sq_direction_t */
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};
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u8 sq_identity;
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};
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u8 _reserved1;
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} ena_aq_destroy_sq_cmd_t;
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typedef struct
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{
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u16 cq_idx;
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u16 _reserved1;
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} ena_aq_destroy_cq_cmd_t;
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STATIC_ASSERT_SIZEOF (ena_aq_create_sq_cmd_t, 32);
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STATIC_ASSERT_SIZEOF (ena_aq_create_sq_resp_t, 16);
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STATIC_ASSERT_SIZEOF (ena_aq_create_cq_cmd_t, 16);
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STATIC_ASSERT_SIZEOF (ena_aq_create_cq_resp_t, 16);
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STATIC_ASSERT_SIZEOF (ena_aq_destroy_sq_cmd_t, 4);
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STATIC_ASSERT_SIZEOF (ena_aq_destroy_cq_cmd_t, 4);
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typedef struct
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{
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/* common desc */
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u16 command_id;
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ena_aq_opcode_t opcode;
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union
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{
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struct
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{
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u8 phase : 1;
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u8 ctrl_data : 1;
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u8 ctrl_data_indirect : 1;
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u8 _reserved_3_3 : 5;
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};
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u8 flags;
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};
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u32 data[15];
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} ena_aq_sq_entry_t;
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STATIC_ASSERT_SIZEOF (ena_aq_sq_entry_t, 64);
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|
typedef struct
|
|
{
|
|
u32 os_type;
|
|
u8 os_dist_str[128];
|
|
u32 os_dist;
|
|
u8 kernel_ver_str[32];
|
|
u32 kernel_ver;
|
|
|
|
struct
|
|
{
|
|
u8 major;
|
|
u8 minor;
|
|
u8 sub_minor;
|
|
u8 module_type;
|
|
} driver_version;
|
|
|
|
u32 supported_network_features[2];
|
|
|
|
struct
|
|
{
|
|
u16 minor : 8;
|
|
u16 major : 8;
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|
} ena_spec_version;
|
|
|
|
struct
|
|
{
|
|
u16 function : 3;
|
|
u16 device : 5;
|
|
u16 bus : 8;
|
|
} bdf;
|
|
|
|
u16 num_cpus;
|
|
u16 _reserved;
|
|
|
|
union
|
|
{
|
|
struct
|
|
{
|
|
u32 _reserved0 : 1;
|
|
u32 rx_offset : 1;
|
|
u32 interrupt_moderation : 1;
|
|
u32 rx_buf_mirroring : 1;
|
|
u32 rss_configurable_function_key : 1;
|
|
u32 _reserved5 : 1;
|
|
u32 rx_page_reuse : 1;
|
|
u32 tx_ipv6_csum_offload : 1;
|
|
u32 _reserved8 : 24;
|
|
};
|
|
u32 as_u32;
|
|
} driver_supported_features;
|
|
|
|
} ena_aq_host_info_t;
|
|
|
|
STATIC_ASSERT_SIZEOF (ena_aq_host_info_t, 196);
|
|
|
|
typedef struct
|
|
{
|
|
union
|
|
{
|
|
u64 tx_bytes;
|
|
struct
|
|
{
|
|
u32 tx_bytes_low;
|
|
u32 tx_bytes_high;
|
|
};
|
|
};
|
|
union
|
|
{
|
|
u64 tx_pkts;
|
|
struct
|
|
{
|
|
u32 tx_pkts_low;
|
|
u32 tx_pkts_high;
|
|
};
|
|
};
|
|
union
|
|
{
|
|
u64 rx_bytes;
|
|
struct
|
|
{
|
|
u32 rx_bytes_low;
|
|
u32 rx_bytes_high;
|
|
};
|
|
};
|
|
union
|
|
{
|
|
u64 rx_pkts;
|
|
struct
|
|
{
|
|
u32 rx_pkts_low;
|
|
u32 rx_pkts_high;
|
|
};
|
|
};
|
|
union
|
|
{
|
|
u64 rx_drops;
|
|
struct
|
|
{
|
|
u32 rx_drops_low;
|
|
u32 rx_drops_high;
|
|
};
|
|
};
|
|
union
|
|
{
|
|
u64 tx_drops;
|
|
struct
|
|
{
|
|
u32 tx_drops_low;
|
|
u32 tx_drops_high;
|
|
};
|
|
};
|
|
} ena_aq_basic_stats_t;
|
|
|
|
#define foreach_ena_aq_basic_counter \
|
|
_ (rx_pkts, "RX Packets") \
|
|
_ (tx_pkts, "TX Packets") \
|
|
_ (rx_bytes, "RX Bytes") \
|
|
_ (tx_bytes, "TX Bytes") \
|
|
_ (rx_drops, "RX Packet Drops") \
|
|
_ (tx_drops, "TX Packet Drops")
|
|
|
|
typedef struct
|
|
{
|
|
u64 bw_in_allowance_exceeded;
|
|
u64 bw_out_allowance_exceeded;
|
|
u64 pps_allowance_exceeded;
|
|
u64 conntrack_allowance_exceeded;
|
|
u64 linklocal_allowance_exceeded;
|
|
} ena_aq_eni_stats_t;
|
|
|
|
#define foreach_ena_aq_eni_counter \
|
|
_ (bw_in_allowance_exceeded, "Input BW Allowance Exceeded") \
|
|
_ (bw_out_allowance_exceeded, "Output BW Allowance Exceeded") \
|
|
_ (pps_allowance_exceeded, "PPS Allowance Exceeded") \
|
|
_ (conntrack_allowance_exceeded, "ConnTrack Allowance Exceeded") \
|
|
_ (linklocal_allowance_exceeded, "LinkLocal Allowance Exceeded")
|
|
|
|
typedef struct
|
|
{
|
|
/* common desc */
|
|
u16 command;
|
|
ena_aq_compl_status_t status;
|
|
union
|
|
{
|
|
struct
|
|
{
|
|
u8 phase : 1;
|
|
u8 _reserved3_1 : 7;
|
|
};
|
|
u8 flags;
|
|
};
|
|
u16 extended_status;
|
|
u16 sq_head_indx;
|
|
|
|
u32 data[14];
|
|
} ena_aq_cq_entry_t;
|
|
|
|
STATIC_ASSERT_SIZEOF (ena_aq_cq_entry_t, 64);
|
|
|
|
#endif /* _ENA_ADMIN_DEFS_H_ */
|