7cd468a3d7
Change-Id: I7b51f88292e057c6443b12224486f2d0c9f8ae23 Signed-off-by: Damjan Marion <damarion@cisco.com>
126 lines
2.9 KiB
C
126 lines
2.9 KiB
C
/*
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* Copyright (c) 2015 Cisco and/or its affiliates.
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef included_asm_x86_h
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#define included_asm_x86_h
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#include <vppinfra/format.h>
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typedef union
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{
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struct
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{
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u8 code;
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u8 type;
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};
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u8 data[2];
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} x86_insn_operand_t;
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typedef struct
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{
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/* Instruction name. */
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char *name;
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/* X86 instructions may have up to 3 operands. */
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x86_insn_operand_t operands[3];
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u16 flags;
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#define X86_INSN_FLAG_DEFAULT_64_BIT (1 << 0)
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#define X86_INSN_FLAG_SET_SSE_GROUP(n) ((n) << 5)
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#define X86_INSN_FLAG_GET_SSE_GROUP(f) (((f) >> 5) & 0x1f)
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#define X86_INSN_FLAG_SET_MODRM_REG_GROUP(n) (((n) & 0x3f) << 10)
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#define X86_INSN_FLAG_GET_MODRM_REG_GROUP(f) (((f) >> 10) & 0x3f)
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} x86_insn_t;
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always_inline uword
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x86_insn_operand_is_valid (x86_insn_t * i, uword o)
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{
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ASSERT (o < ARRAY_LEN (i->operands));
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return i->operands[o].code != '_';
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}
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#define foreach_x86_legacy_prefix \
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_ (OPERAND_SIZE, 0x66) \
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_ (ADDRESS_SIZE, 0x67) \
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_ (SEGMENT_CS, 0x2e) \
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_ (SEGMENT_DS, 0x3e) \
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_ (SEGMENT_ES, 0x26) \
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_ (SEGMENT_FS, 0x64) \
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_ (SEGMENT_GS, 0x65) \
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_ (SEGMENT_SS, 0x36) \
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_ (LOCK, 0xf0) \
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_ (REPZ, 0xf3) \
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_ (REPNZ, 0xf2)
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#define foreach_x86_insn_parse_flag \
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/* Parse in 32/64-bit mode. */ \
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_ (PARSE_32_BIT, 0) \
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_ (PARSE_64_BIT, 0) \
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_ (IS_ADDRESS, 0) \
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/* regs[1/2] is a valid base/index register */ \
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_ (HAS_BASE, 0) \
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_ (HAS_INDEX, 0) \
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/* rex w bit */ \
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_ (OPERAND_SIZE_64, 0)
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typedef enum
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{
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#define _(f,o) X86_INSN_FLAG_BIT_##f,
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foreach_x86_insn_parse_flag foreach_x86_legacy_prefix
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#undef _
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} x86_insn_parse_flag_bit_t;
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typedef enum
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{
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#define _(f,o) X86_INSN_##f = 1 << X86_INSN_FLAG_BIT_##f,
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foreach_x86_insn_parse_flag foreach_x86_legacy_prefix
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#undef _
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} x86_insn_parse_flag_t;
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typedef struct
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{
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/* Registers in instruction.
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[0] is modrm reg field
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[1] is base reg
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[2] is index reg. */
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u8 regs[3];
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/* Scale for index register. */
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u8 log2_index_scale:2;
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u8 log2_effective_operand_bytes:3;
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u8 log2_effective_address_bytes:3;
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i32 displacement;
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/* Parser flags: set of x86_insn_parse_flag_t enums. */
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u32 flags;
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i64 immediate;
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x86_insn_t insn;
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} x86_insn_parse_t;
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u8 *x86_insn_parse (x86_insn_parse_t * p, u8 * code_start);
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format_function_t format_x86_insn_parse;
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#endif /* included_asm_x86_h */
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/*
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* fd.io coding-style-patch-verification: ON
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*
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* Local Variables:
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* eval: (c-set-style "gnu")
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* End:
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*/
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