67f03ba71d
Type: improvement Change-Id: Ie5fcaa706ab0995e0021cf1ee74b95c5a3b30283 Signed-off-by: Damjan Marion <damarion@cisco.com>
365 lines
22 KiB
C
365 lines
22 KiB
C
/* SPDX-License-Identifier: Apache-2.0
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* Copyright (c) 2023 Cisco Systems, Inc.
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*/
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#ifndef _IIAVF_REGS_H_
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#define _IIAVF_REGS_H_
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#include <vppinfra/clib.h>
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#include <vppinfra/error_bootstrap.h>
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#include <vppinfra/format.h>
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#include <vnet/vnet.h>
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#include <vnet/dev/dev.h>
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#define iavf_reg_ctrl_t_fields \
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__ (1, full_duplex) \
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__ (1, _reserved1) \
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__ (1, gio_master_disable) \
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__ (3, _reserved3) \
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__ (1, set_link_up) \
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__ (9, _reserved7) \
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__ (1, sdp0_gpien) \
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__ (1, sdp1_gpien) \
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__ (1, sdp0_data) \
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__ (1, sdp1_data) \
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__ (1, adww3wuc) \
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__ (1, sdp0_wde) \
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__ (1, sdp0_iodir) \
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__ (1, sdp1_iodir) \
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__ (2, _reserved24) \
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__ (1, port_sw_reset) \
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__ (1, rx_flow_ctl_en) \
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__ (1, tx_flow_ctl_en) \
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__ (1, device_reset) \
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__ (1, vlan_mode_enable) \
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__ (1, phy_reset)
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#define iavf_reg_status_t_fields \
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__ (1, full_duplex) \
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__ (1, link_up) \
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__ (2, _reserved2) \
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__ (1, tx_off) \
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__ (1, _reserved5) \
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__ (2, speed) \
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__ (2, asdv) \
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__ (1, phy_reset_asserted) \
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__ (8, _reserved11) \
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__ (1, gio_master_en_sts) \
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__ (1, dev_rst_set) \
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__ (1, rst_done) \
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__ (1, speed_2p5) \
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__ (7, _reserved23) \
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__ (1, lpi_ignore) \
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__ (1, _reserved31)
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#define iavf_reg_ctrl_ext_t_fields \
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__ (2, _reserved0) \
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__ (1, sdp2_gpien) \
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__ (1, sdp3_gpien) \
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__ (2, _reserved4) \
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__ (1, sdp2_data) \
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__ (1, sdp3_data) \
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__ (2, _reserved8) \
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__ (1, sdp2_iodir) \
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__ (1, sdp3_iodir) \
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__ (1, _reserved12) \
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__ (1, eeprom_block_rst) \
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__ (2, _reserved14) \
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__ (1, no_snoop_dis) \
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__ (1, relaxed_ordering_dis) \
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__ (2, _reserved18) \
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__ (1, phy_power_down_ena) \
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__ (5, _reserved121) \
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__ (1, ext_vlan_ena) \
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__ (1, _reserved127) \
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__ (1, driver_loaded) \
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__ (3, _reserved29)
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#define iavf_reg_mdic_t_fields \
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__ (16, data) \
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__ (5, regadd) \
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__ (5, _reserved21) \
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__ (2, opcode) \
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__ (1, ready) \
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__ (1, mid_ie) \
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__ (1, mid_err) \
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__ (1, _reserved31)
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#define iavf_reg_rctl_t_fields \
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__ (1, _reserved0) \
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__ (1, rx_enable) \
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__ (1, store_bad_packets) \
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__ (1, uc_promisc_ena) \
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__ (1, mc_promisc_ena) \
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__ (1, long_pkt_reception_ena) \
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__ (2, loopback_mode) \
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__ (2, hash_select) \
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__ (2, _reserved10) \
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__ (2, mc_uc_tbl_off) \
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__ (1, _reserved14) \
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__ (1, bcast_accept_mode) \
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__ (2, rx_buf_sz) \
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__ (1, vlan_filter_ena) \
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__ (1, cannonical_form_ind_ena) \
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__ (1, cannonical_form_ind_bit_val) \
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__ (1, pad_small_rx_pkts) \
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__ (1, discard_pause_frames) \
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__ (1, pass_mac_ctrl_frames) \
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__ (2, _reserved24) \
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__ (1, strip_eth_crc) \
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__ (5, _reserved26)
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#define iavf_reg_tctl_t_fields \
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__ (1, _reserved0) \
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__ (1, tx_enable) \
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__ (1, _reserved2) \
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__ (1, pad_short_pkts) \
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__ (8, collision_threshold) \
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__ (10, backoff_slot_time) \
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__ (1, sw_xoff_tx) \
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__ (1, _reserved23) \
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__ (1, retransmit_on_late_colision) \
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__ (7, reserved25)
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#define iavf_reg_phpm_t_fields \
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__ (1, _reserved0) \
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__ (1, restart_autoneg) \
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__ (1, _reserved2) \
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__ (1, dis_1000_in_non_d0a) \
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__ (1, link_energy_detect) \
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__ (1, go_link_disc) \
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__ (1, disable_1000) \
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__ (1, spd_b2b_en) \
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__ (1, rst_compl) \
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__ (1, dis_100_in_non_d0a) \
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__ (1, ulp_req) \
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__ (1, disable_2500) \
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__ (1, dis_2500_in_non_d0a) \
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__ (1, ulp_trig) \
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__ (2, ulp_delay) \
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__ (1, link_enery_en) \
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__ (1, dev_off_en) \
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__ (1, dev_off_state) \
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__ (1, ulp_en) \
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__ (12, _reserved20)
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#define iavf_reg_manc_t_fields \
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__ (1, flow_ctrl_discard) \
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__ (1, ncsi_discard) \
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__ (12, _reserved2) \
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__ (1, fw_reset) \
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__ (1, tco_isolate) \
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__ (1, tco_reset) \
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__ (1, rcv_tco_en) \
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__ (1, keep_phy_link_up) \
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__ (1, rcv_all) \
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__ (1, inhibit_ulp) \
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__ (2, _reserved21) \
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__ (1, en_xsum_filter) \
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__ (1, en_ipv4_filter) \
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__ (1, fixed_net_type) \
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__ (1, net_type) \
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__ (1, ipv6_adv_only) \
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__ (1, en_bmc2os) \
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__ (1, en_bmc2net) \
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__ (1, mproxye) \
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__ (1, mproxya)
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#define iavf_reg_swsm_t_fields \
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__ (1, smbi) \
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__ (1, swesmbi) \
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__ (30, _reserved2)
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#define iavf_reg_fwsm_t_fields \
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__ (1, eep_fw_semaphore) \
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__ (3, fw_mode) \
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__ (2, _reserved4) \
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__ (1, eep_reload_ind) \
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__ (8, _reserved7) \
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__ (1, fw_val_bit) \
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__ (3, reset_ctr) \
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__ (6, ext_err_ind) \
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__ (1, pcie_config_err_ind) \
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__ (5, _reserved26) \
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__ (1, factory_mac_addr_restored)
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#define iavf_reg_sw_fw_sync_t_fields \
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__ (1, sw_flash_sm) \
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__ (1, sw_phy_sm) \
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__ (1, sw_i2c_sm) \
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__ (1, sw_mac_csr_sm) \
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__ (3, _reserved4) \
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__ (1, sw_svr_sm) \
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__ (1, sw_mb_sm) \
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__ (1, _reserved9) \
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__ (1, sw_mng_sm) \
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__ (5, _reserved11) \
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__ (1, fw_flash_sm) \
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__ (1, fw_phy_sm) \
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__ (1, fw_i2c_sm) \
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__ (1, fw_mac_csr_sm) \
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__ (3, _reserved20) \
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__ (1, fw_svr_sm) \
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__ (8, _reserved24)
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#define iavf_reg_srrctl_t_fields \
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__ (7, bsizepacket) \
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__ (1, _reserved7) \
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__ (6, bsizeheader) \
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__ (2, timer1_sel) \
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__ (1, _reserved16) \
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__ (2, timer0_sel) \
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__ (1, use_domain) \
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__ (5, rdmts) \
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__ (3, desc_type) \
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__ (2, _reserved28) \
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__ (1, timestamp) \
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__ (1, drop_en)
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#define iavf_reg_rxdctl_t_fields \
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__ (5, pthresh) \
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__ (3, _reserved5) \
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__ (5, hthresh) \
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__ (3, _reserved13) \
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__ (5, wthresh) \
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__ (4, _reserved21) \
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__ (1, enable) \
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__ (1, swflush) \
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__ (5, _reserved27)
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#define iavf_reg_eec_t_fields \
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__ (6, _reserved0) \
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__ (1, flash_in_use) \
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__ (1, _reserved7) \
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__ (1, ee_pres) \
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__ (1, auto_rd) \
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__ (1, _reservedxi10) \
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__ (4, ee_size) \
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__ (4, pci_ana_done) \
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__ (1, flash_detected) \
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__ (2, _reserved20) \
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__ (1, shadow_modified) \
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__ (1, flupd) \
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__ (1, _reserved24) \
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__ (1, sec1val) \
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__ (1, fludone) \
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__ (5, _reserved27)
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#define iavf_reg_eemngctl_t_fields \
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__ (11, addr) \
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__ (4, reserved11) \
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__ (1, cmd_valid) \
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__ (1, write) \
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__ (1, eebusy) \
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__ (1, cfg_done) \
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__ (12, _reserved19) \
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__ (1, done)
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#define IAVF_REG_STRUCT(n) \
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typedef union \
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{ \
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struct \
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{ \
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n##_fields; \
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}; \
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u32 as_u32; \
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} n; \
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STATIC_ASSERT_SIZEOF (n, 4);
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#define __(n, f) u32 f : n;
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IAVF_REG_STRUCT (iavf_reg_status_t);
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IAVF_REG_STRUCT (iavf_reg_ctrl_t);
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IAVF_REG_STRUCT (iavf_reg_ctrl_ext_t);
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IAVF_REG_STRUCT (iavf_reg_mdic_t);
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IAVF_REG_STRUCT (iavf_reg_rctl_t);
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IAVF_REG_STRUCT (iavf_reg_tctl_t);
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IAVF_REG_STRUCT (iavf_reg_phpm_t);
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IAVF_REG_STRUCT (iavf_reg_manc_t);
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IAVF_REG_STRUCT (iavf_reg_swsm_t);
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IAVF_REG_STRUCT (iavf_reg_fwsm_t);
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IAVF_REG_STRUCT (iavf_reg_sw_fw_sync_t);
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IAVF_REG_STRUCT (iavf_reg_srrctl_t);
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IAVF_REG_STRUCT (iavf_reg_rxdctl_t);
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IAVF_REG_STRUCT (iavf_reg_eec_t);
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IAVF_REG_STRUCT (iavf_reg_eemngctl_t);
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#undef __
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#define foreach_iavf_reg \
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_ (0x00000, CTRL, iavf_reg_ctrl_t_fields) \
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_ (0x00008, STATUS, iavf_reg_status_t_fields) \
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_ (0x00018, CTRL_EXT, iavf_reg_ctrl_ext_t_fields) \
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_ (0x00020, MDIC, iavf_reg_mdic_t_fields) \
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_ (0x00100, RCTL, iavf_reg_rctl_t_fields) \
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_ (0x00400, TCTL, iavf_reg_tctl_t_fields) \
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_ (0x00404, TCTL_EXT, ) \
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_ (0x00e14, PHPM, iavf_reg_phpm_t_fields) \
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_ (0x01500, ICR, ) \
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_ (0x0150c, IMC, ) \
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_ (0x05400, RAL0, ) \
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_ (0x05404, RAH0, ) \
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_ (0x05820, MANC, iavf_reg_manc_t_fields) \
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_ (0x05b50, SWSM, iavf_reg_swsm_t_fields) \
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_ (0x05b54, FWSM, iavf_reg_fwsm_t_fields) \
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_ (0x05b5c, SW_FW_SYNC, iavf_reg_sw_fw_sync_t_fields) \
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_ (0x0c000, RDBAL0, ) \
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_ (0x0c004, RDBAH0, ) \
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_ (0x0c008, RDLEN0, ) \
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_ (0x0c00c, SRRCTL0, iavf_reg_srrctl_t_fields) \
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_ (0x0c010, RDH0, ) \
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_ (0x0c018, RDT0, ) \
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_ (0x0c028, RXDCTL0, iavf_reg_rxdctl_t_fields) \
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_ (0x12010, EEC, iavf_reg_eec_t_fields) \
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_ (0x12030, EEMNGCTL, iavf_reg_eemngctl_t_fields)
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#define IAVF_REG_RDBAL(n) (IAVF_REG_RDBAL0 + (n) *0x40)
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#define IAVF_REG_RDBAH(n) (IAVF_REG_RDBAH0 + (n) *0x40)
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#define IAVF_REG_RDLEN(n) (IAVF_REG_RDLEN0 + (n) *0x40)
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#define IAVF_REG_SRRCTL(n) (IAVF_REG_SRRCTL0 + (n) *0x40)
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#define IAVF_REG_RDH(n) (IAVF_REG_RDH0 + (n) *0x40)
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#define IAVF_REG_RDT(n) (IAVF_REG_RDT0 + (n) *0x40)
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#define IAVF_REG_RXDCTL(n) (IAVF_REG_RXDCTL0 + (n) *0x40)
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#define IAVF_REG_SRRCTL(n) (IAVF_REG_SRRCTL0 + (n) *0x40)
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typedef enum
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{
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#define _(o, n, f) IAVF_REG_##n = (o),
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foreach_iavf_reg
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#undef _
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} iavf_reg_t;
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typedef union
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{
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struct
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{
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u32 intena : 1;
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u32 clearpba : 1;
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u32 swint_trig : 1;
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u32 itr_indx : 2;
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u32 interval : 12;
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u32 _rsvd23 : 7;
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u32 sw_itr_indx_ena : 1;
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u32 sw_itr_indx : 2;
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u32 _rsvd29 : 3;
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u32 wb_on_itr : 1;
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u32 intena_msk : 1;
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};
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u32 as_u32;
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} iavf_dyn_ctl;
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STATIC_ASSERT_SIZEOF (iavf_dyn_ctl, 4);
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typedef union
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{
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struct
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{
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u32 _reserved0 : 30;
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u32 adminq : 1;
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u32 _reserved31 : 1;
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};
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u32 as_u32;
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} iavf_vfint_icr0_ena1;
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STATIC_ASSERT_SIZEOF (iavf_vfint_icr0_ena1, 4);
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#endif /* _IIAVF_REGS_H_ */
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