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update 2D idwt to not assign zero to the last element of cDTemp

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This commit is contained in:
Samuel Li 2016-10-24 19:11:05 -07:00
parent 568bd63fbe
commit d7e94e3ad5
2 changed files with 14 additions and 9 deletions
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21
vtkm/worklet/wavelets/WaveletDWT.h
View File

@ -163,12 +163,19 @@ public:
ext2Method, dir, false );
DispatcherType dispatcher( worklet );
dispatcher.Invoke( ext2, sigIn );
if( modeLR )
WaveletBase::DeviceAssignZero2DColumn( ext2, extDimX, extDimY,
extDimX-1, DeviceTag() );
else
WaveletBase::DeviceAssignZero2DRow( ext2, extDimX, extDimY,
extDimY-1, DeviceTag() );
/* Pad a zero at the end of cDTemp, when cDTemp is forced to have the same
length as cATemp. For example, with odd length signal, cA is 1 element
longer than cD.
*/
/* Update 10/24/2016: the extra element of cD shouldn't be zero, just be
* whatever it extends to be.
* if( modeLR )
* WaveletBase::DeviceAssignZero2DColumn( ext2, extDimX, extDimY,
* extDimX-1, DeviceTag() );
* else
* WaveletBase::DeviceAssignZero2DRow( ext2, extDimX, extDimY,
* extDimY-1, DeviceTag() );
*/
}
else // pretendSigPaddedZero
{
@ -804,8 +811,6 @@ public:
vtkm::Id inDimY,
vtkm::Id inStartX,
vtkm::Id inStartY,
//vtkm::Id inPretendDimX,
//vtkm::Id inPretendDimY,
const std::vector<vtkm::Id> &L,
ArrayOutType &sigOut,
DeviceTag )

2
vtkm/worklet/wavelets/WaveletTransforms.h
View File

@ -1450,7 +1450,7 @@ public:
{
vtkm::Id x, y;
GetLogicalDim( workIdx, x, y );
if( zeroY < 0 && x == zeroX ) // assign zero to a column
if( zeroY < 0 && x == zeroX ) // assign zero to a column
array.Set( workIdx, static_cast<typename PortalType::ValueType>(0.0) );
else if( zeroX < 0 && y == zeroY ) // assign zero to a row
array.Set( workIdx, static_cast<typename PortalType::ValueType>(0.0) );