commit
4570187459
@ -52,7 +52,8 @@ public:
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ARCH_ZEN_PLUS,
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ARCH_ZEN2,
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ARCH_ZEN3,
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ARCH_ZEN4
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ARCH_ZEN4,
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ARCH_ZEN5
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};
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enum MsrMod : uint32_t {
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@ -60,12 +61,13 @@ public:
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MSR_MOD_RYZEN_17H,
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MSR_MOD_RYZEN_19H,
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MSR_MOD_RYZEN_19H_ZEN4,
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MSR_MOD_RYZEN_1AH_ZEN5,
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MSR_MOD_INTEL,
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MSR_MOD_CUSTOM,
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MSR_MOD_MAX
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};
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# define MSR_NAMES_LIST "none", "ryzen_17h", "ryzen_19h", "ryzen_19h_zen4", "intel", "custom"
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# define MSR_NAMES_LIST "none", "ryzen_17h", "ryzen_19h", "ryzen_19h_zen4", "ryzen_1Ah_zen5", "intel", "custom"
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enum Flag : uint32_t {
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FLAG_AES,
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@ -64,7 +64,7 @@ static_assert(kCpuFlagsSize == ICpuInfo::FLAG_MAX, "kCpuFlagsSize and FLAG_MAX m
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#ifdef XMRIG_FEATURE_MSR
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constexpr size_t kMsrArraySize = 6;
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constexpr size_t kMsrArraySize = 7;
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static const std::array<const char *, kMsrArraySize> msrNames = { MSR_NAMES_LIST };
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static_assert(kMsrArraySize == ICpuInfo::MSR_MOD_MAX, "kMsrArraySize and MSR_MOD_MAX mismatch");
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#endif
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@ -260,6 +260,11 @@ xmrig::BasicCpuInfo::BasicCpuInfo() :
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}
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break;
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case 0x1a:
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m_arch = ARCH_ZEN5;
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m_msrMod = MSR_MOD_RYZEN_1AH_ZEN5;
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break;
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default:
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m_msrMod = MSR_MOD_NONE;
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break;
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@ -266,6 +266,10 @@ namespace randomx {
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// AVX2 init is slower on Zen4
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initDatasetAVX2 = false;
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break;
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case xmrig::ICpuInfo::ARCH_ZEN5:
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// TODO: test it
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initDatasetAVX2 = false;
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break;
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}
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}
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}
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@ -53,13 +53,17 @@ static const std::array<const char *, RxConfig::ModeMax> modeNames = { "auto", "
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#ifdef XMRIG_FEATURE_MSR
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constexpr size_t kMsrArraySize = 6;
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constexpr size_t kMsrArraySize = 7;
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static const std::array<MsrItems, kMsrArraySize> msrPresets = {
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MsrItems(),
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MsrItems{{ 0xC0011020, 0ULL }, { 0xC0011021, 0x40ULL, ~0x20ULL }, { 0xC0011022, 0x1510000ULL }, { 0xC001102b, 0x2000cc16ULL }},
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MsrItems{{ 0xC0011020, 0x0004480000000000ULL }, { 0xC0011021, 0x001c000200000040ULL, ~0x20ULL }, { 0xC0011022, 0xc000000401570000ULL }, { 0xC001102b, 0x2000cc10ULL }},
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MsrItems{{ 0xC0011020, 0x0004400000000000ULL }, { 0xC0011021, 0x0004000000000040ULL, ~0x20ULL }, { 0xC0011022, 0x8680000401570000ULL }, { 0xC001102b, 0x2040cc10ULL }},
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// TODO: Tune it for Zen5 when it's available
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MsrItems{{ 0xC0011020, 0x0004400000000000ULL }, { 0xC0011021, 0x0004000000000040ULL, ~0x20ULL }, { 0xC0011022, 0x8680000401570000ULL }, { 0xC001102b, 0x2040cc10ULL }},
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MsrItems{{ 0x1a4, 0xf }},
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MsrItems()
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};
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