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Merge pull request #3525 from SChernykh/dev

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Added Zen5 detection
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xmrig 2024-08-03 22:58:00 +07:00 committed by GitHub
commit 4570187459
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GPG Key ID: B5690EEEBB952194
4 changed files with 19 additions and 4 deletions
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6
src/backend/cpu/interfaces/ICpuInfo.h
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@ -52,7 +52,8 @@ public:
ARCH_ZEN_PLUS, ARCH_ZEN_PLUS,
ARCH_ZEN2, ARCH_ZEN2,
ARCH_ZEN3, ARCH_ZEN3,
ARCH_ZEN4 ARCH_ZEN4,
ARCH_ZEN5
}; };
enum MsrMod : uint32_t { enum MsrMod : uint32_t {
@ -60,12 +61,13 @@ public:
MSR_MOD_RYZEN_17H, MSR_MOD_RYZEN_17H,
MSR_MOD_RYZEN_19H, MSR_MOD_RYZEN_19H,
MSR_MOD_RYZEN_19H_ZEN4, MSR_MOD_RYZEN_19H_ZEN4,
MSR_MOD_RYZEN_1AH_ZEN5,
MSR_MOD_INTEL, MSR_MOD_INTEL,
MSR_MOD_CUSTOM, MSR_MOD_CUSTOM,
MSR_MOD_MAX MSR_MOD_MAX
}; };
# define MSR_NAMES_LIST "none", "ryzen_17h", "ryzen_19h", "ryzen_19h_zen4", "intel", "custom" # define MSR_NAMES_LIST "none", "ryzen_17h", "ryzen_19h", "ryzen_19h_zen4", "ryzen_1Ah_zen5", "intel", "custom"
enum Flag : uint32_t { enum Flag : uint32_t {
FLAG_AES, FLAG_AES,

7
src/backend/cpu/platform/BasicCpuInfo.cpp
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@ -64,7 +64,7 @@ static_assert(kCpuFlagsSize == ICpuInfo::FLAG_MAX, "kCpuFlagsSize and FLAG_MAX m
#ifdef XMRIG_FEATURE_MSR #ifdef XMRIG_FEATURE_MSR
constexpr size_t kMsrArraySize = 6; constexpr size_t kMsrArraySize = 7;
static const std::array<const char *, kMsrArraySize> msrNames = { MSR_NAMES_LIST }; static const std::array<const char *, kMsrArraySize> msrNames = { MSR_NAMES_LIST };
static_assert(kMsrArraySize == ICpuInfo::MSR_MOD_MAX, "kMsrArraySize and MSR_MOD_MAX mismatch"); static_assert(kMsrArraySize == ICpuInfo::MSR_MOD_MAX, "kMsrArraySize and MSR_MOD_MAX mismatch");
#endif #endif
@ -260,6 +260,11 @@ xmrig::BasicCpuInfo::BasicCpuInfo() :
} }
break; break;
case 0x1a:
m_arch = ARCH_ZEN5;
m_msrMod = MSR_MOD_RYZEN_1AH_ZEN5;
break;
default: default:
m_msrMod = MSR_MOD_NONE; m_msrMod = MSR_MOD_NONE;
break; break;

4
src/crypto/randomx/jit_compiler_x86.cpp
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@ -266,6 +266,10 @@ namespace randomx {
// AVX2 init is slower on Zen4 // AVX2 init is slower on Zen4
initDatasetAVX2 = false; initDatasetAVX2 = false;
break; break;
case xmrig::ICpuInfo::ARCH_ZEN5:
// TODO: test it
initDatasetAVX2 = false;
break;
} }
} }
} }

6
src/crypto/rx/RxConfig.cpp
View File

@ -53,13 +53,17 @@ static const std::array<const char *, RxConfig::ModeMax> modeNames = { "auto", "
#ifdef XMRIG_FEATURE_MSR #ifdef XMRIG_FEATURE_MSR
constexpr size_t kMsrArraySize = 6; constexpr size_t kMsrArraySize = 7;
static const std::array<MsrItems, kMsrArraySize> msrPresets = { static const std::array<MsrItems, kMsrArraySize> msrPresets = {
MsrItems(), MsrItems(),
MsrItems{{ 0xC0011020, 0ULL }, { 0xC0011021, 0x40ULL, ~0x20ULL }, { 0xC0011022, 0x1510000ULL }, { 0xC001102b, 0x2000cc16ULL }}, MsrItems{{ 0xC0011020, 0ULL }, { 0xC0011021, 0x40ULL, ~0x20ULL }, { 0xC0011022, 0x1510000ULL }, { 0xC001102b, 0x2000cc16ULL }},
MsrItems{{ 0xC0011020, 0x0004480000000000ULL }, { 0xC0011021, 0x001c000200000040ULL, ~0x20ULL }, { 0xC0011022, 0xc000000401570000ULL }, { 0xC001102b, 0x2000cc10ULL }}, MsrItems{{ 0xC0011020, 0x0004480000000000ULL }, { 0xC0011021, 0x001c000200000040ULL, ~0x20ULL }, { 0xC0011022, 0xc000000401570000ULL }, { 0xC001102b, 0x2000cc10ULL }},
MsrItems{{ 0xC0011020, 0x0004400000000000ULL }, { 0xC0011021, 0x0004000000000040ULL, ~0x20ULL }, { 0xC0011022, 0x8680000401570000ULL }, { 0xC001102b, 0x2040cc10ULL }}, MsrItems{{ 0xC0011020, 0x0004400000000000ULL }, { 0xC0011021, 0x0004000000000040ULL, ~0x20ULL }, { 0xC0011022, 0x8680000401570000ULL }, { 0xC001102b, 0x2040cc10ULL }},
// TODO: Tune it for Zen5 when it's available
MsrItems{{ 0xC0011020, 0x0004400000000000ULL }, { 0xC0011021, 0x0004000000000040ULL, ~0x20ULL }, { 0xC0011022, 0x8680000401570000ULL }, { 0xC001102b, 0x2040cc10ULL }},
MsrItems{{ 0x1a4, 0xf }}, MsrItems{{ 0x1a4, 0xf }},
MsrItems() MsrItems()
}; };