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Cater for ECC failures in EFL wear-leveling. (#19749)
Co-authored-by: Sergey Vlasov <sigprof@gmail.com>
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parent
3ef06aa732
commit
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@ -17,6 +17,9 @@ static flash_sector_t first_sector = UINT16_MAX;
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static flash_sector_t sector_count = UINT16_MAX;
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static BaseFlash * flash;
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static volatile bool is_issuing_read = false;
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static volatile bool ecc_error_occurred = false;
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// "Automatic" detection of the flash size -- ideally ChibiOS would have this already, but alas, it doesn't.
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static inline uint32_t detect_flash_size(void) {
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#if defined(WEAR_LEVELING_EFL_FLASH_SIZE)
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@ -131,11 +134,38 @@ bool backing_store_lock(void) {
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return true;
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}
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static backing_store_int_t backing_store_safe_read_from_location(backing_store_int_t *loc) {
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backing_store_int_t value;
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is_issuing_read = true;
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ecc_error_occurred = false;
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value = ~(*loc);
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is_issuing_read = false;
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return value;
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}
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bool backing_store_read(uint32_t address, backing_store_int_t *value) {
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uint32_t offset = (base_offset + address);
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backing_store_int_t *loc = (backing_store_int_t *)flashGetOffsetAddress(flash, offset);
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*value = ~(*loc);
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backing_store_int_t tmp = backing_store_safe_read_from_location(loc);
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if (ecc_error_occurred) {
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bs_dprintf("Failed to read from backing store, ECC error detected\n");
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ecc_error_occurred = false;
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*value = 0;
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return false;
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}
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*value = tmp;
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bs_dprintf("Read ");
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wl_dump(offset, value, sizeof(backing_store_int_t));
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return true;
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}
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bool backing_store_allow_ecc_errors(void) {
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return is_issuing_read;
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}
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void backing_store_signal_ecc_error(void) {
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ecc_error_occurred = true;
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}
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45
platforms/chibios/interrupt_handlers.c
Normal file
45
platforms/chibios/interrupt_handlers.c
Normal file
@ -0,0 +1,45 @@
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// Copyright 2023 Nick Brassel (@tzarc)
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// SPDX-License-Identifier: GPL-2.0-or-later
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///////////////////////////////////////////////////////////////////////////////
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// BEGIN: STM32 EFL Wear-leveling ECC fault handling
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//
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// Some STM32s have ECC checks for all flash memory access. Whenever there's an
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// ECC failure, the MCU raises the NMI interrupt. Whenever we receive such an
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// interrupt whilst reading the wear-leveling EEPROM area, we gracefully cater
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// for it, signalling the wear-leveling code that a failure has occurred.
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///////////////////////////////////////////////////////////////////////////////
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#include <ch.h>
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#include <chcore.h>
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#ifdef WEAR_LEVELING_EMBEDDED_FLASH
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# ifdef QMK_MCU_SERIES_STM32L4XX
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# define ECC_ERRORS_TRIGGER_NMI_INTERRUPT
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# define ECC_CHECK_REGISTER FLASH->ECCR
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# define ECC_CHECK_FLAG FLASH_ECCR_ECCD
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# endif // QMK_MCU_SERIES_STM32L4XX
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#endif // WEAR_LEVELING_EMBEDDED_FLASH
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#ifdef ECC_ERRORS_TRIGGER_NMI_INTERRUPT
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extern bool backing_store_allow_ecc_errors(void);
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extern void backing_store_signal_ecc_error(void);
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void NMI_Handler(void) {
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if ((ECC_CHECK_REGISTER) & (ECC_CHECK_FLAG)) {
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if (backing_store_allow_ecc_errors()) {
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(ECC_CHECK_REGISTER) = (ECC_CHECK_FLAG);
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backing_store_signal_ecc_error();
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return;
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}
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}
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chSysHalt("NMI");
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}
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#endif // ECC_ERRORS_TRIGGER_NMI_INTERRUPT
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///////////////////////////////////////////////////////////////////////////////
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// END: STM32 EFL Wear-leveling ECC fault handling
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///////////////////////////////////////////////////////////////////////////////
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@ -277,7 +277,8 @@ PLATFORM_SRC = \
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$(CHIBIOS)/os/various/syscalls.c \
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$(PLATFORM_COMMON_DIR)/syscall-fallbacks.c \
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$(PLATFORM_COMMON_DIR)/wait.c \
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$(PLATFORM_COMMON_DIR)/synchronization_util.c
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$(PLATFORM_COMMON_DIR)/synchronization_util.c \
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$(PLATFORM_COMMON_DIR)/interrupt_handlers.c
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# Ensure the ASM files are not subjected to LTO -- it'll strip out interrupt handlers otherwise.
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QUANTUM_LIB_SRC += $(STARTUPASM) $(PORTASM) $(OSALASM) $(PLATFORMASM)
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