Add FreeRTOS-Plus directory with new directory structure so it matches the FreeRTOS directory.
This commit is contained in:
Richard Barry
@ -0,0 +1,277 @@
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/*
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* FreeRTOS+UDP V1.0.0 (C) 2013 Real Time Engineers ltd.
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*
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* FreeRTOS+UDP is an add-on component to FreeRTOS. It is not, in itself, part
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* of the FreeRTOS kernel. FreeRTOS+UDP is licensed separately from FreeRTOS,
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* and uses a different license to FreeRTOS. FreeRTOS+UDP uses a dual license
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* model, information on which is provided below:
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*
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* - Open source licensing -
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* FreeRTOS+UDP is a free download and may be used, modified and distributed
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* without charge provided the user adheres to version two of the GNU General
|
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* Public license (GPL) and does not remove the copyright notice or this text.
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* The GPL V2 text is available on the gnu.org web site, and on the following
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* URL: http://www.FreeRTOS.org/gpl-2.0.txt
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*
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* - Commercial licensing -
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* Businesses and individuals who wish to incorporate FreeRTOS+UDP into
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* proprietary software for redistribution in any form must first obtain a
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* (very) low cost commercial license - and in-so-doing support the maintenance,
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* support and further development of the FreeRTOS+UDP product. Commercial
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* licenses can be obtained from http://shop.freertos.org and do not require any
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* source files to be changed.
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*
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* FreeRTOS+UDP is distributed in the hope that it will be useful. You cannot
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* use FreeRTOS+UDP unless you agree that you use the software 'as is'.
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* FreeRTOS+UDP is provided WITHOUT ANY WARRANTY; without even the implied
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* warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. Real Time Engineers Ltd. disclaims all conditions and terms, be they
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* implied, expressed, or statutory.
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*
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* 1 tab == 4 spaces!
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*
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* http://www.FreeRTOS.org
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* http://www.FreeRTOS.org/udp
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*
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*/
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/* Standard includes. */
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#include <stdint.h>
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/* FreeRTOS includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#include "queue.h"
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#include "semphr.h"
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/* Hardware abstraction. */
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#include "FreeRTOS_IO.h"
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/* FreeRTOS+UDP includes. */
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#include "FreeRTOS_UDP_IP.h"
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#include "FreeRTOS_Sockets.h"
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#include "NetworkBufferManagement.h"
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/* Driver includes. */
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#include "lpc17xx_emac.h"
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#include "lpc17xx_pinsel.h"
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/* Demo includes. */
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#include "NetworkInterface.h"
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#if ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES != 1
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#define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eProcessBuffer
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#else
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#define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eConsiderFrameForProcessing( ( pucEthernetBuffer ) )
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#endif
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/* When a packet is ready to be sent, if it cannot be sent immediately then the
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task performing the transmit will block for niTX_BUFFER_FREE_WAIT
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milliseconds. It will do this a maximum of niMAX_TX_ATTEMPTS before giving
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up. */
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#define niTX_BUFFER_FREE_WAIT ( ( portTickType ) 2UL / portTICK_RATE_MS )
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#define niMAX_TX_ATTEMPTS ( 5 )
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/* The length of the queue used to send interrupt status words from the
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interrupt handler to the deferred handler task. */
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#define niINTERRUPT_QUEUE_LENGTH ( 10 )
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/*-----------------------------------------------------------*/
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/*
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* A deferred interrupt handler task that processes
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*/
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static void prvEMACHandlerTask( void *pvParameters );
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/*-----------------------------------------------------------*/
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/* The queue used to communicate Ethernet events with the IP task. */
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extern xQueueHandle xNetworkEventQueue;
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/* The semaphore used to wake the deferred interrupt handler task when an Rx
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interrupt is received. */
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static xSemaphoreHandle xEMACRxEventSemaphore = NULL;
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/*-----------------------------------------------------------*/
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portBASE_TYPE xNetworkInterfaceInitialise( void )
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{
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EMAC_CFG_Type Emac_Config;
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PINSEL_CFG_Type xPinConfig;
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portBASE_TYPE xStatus, xReturn;
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extern uint8_t ucMACAddress[ 6 ];
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/* Enable Ethernet Pins */
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boardCONFIGURE_ENET_PINS( xPinConfig );
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Emac_Config.Mode = EMAC_MODE_AUTO;
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Emac_Config.pbEMAC_Addr = ucMACAddress;
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xStatus = EMAC_Init( &Emac_Config );
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LPC_EMAC->IntEnable &= ~( EMAC_INT_TX_DONE );
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if( xStatus != ERROR )
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{
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vSemaphoreCreateBinary( xEMACRxEventSemaphore );
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configASSERT( xEMACRxEventSemaphore );
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/* The handler task is created at the highest possible priority to
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ensure the interrupt handler can return directly to it. */
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xTaskCreate( prvEMACHandlerTask, ( const signed char * const ) "EMAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );
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/* Enable the interrupt and set its priority to the minimum
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interrupt priority. */
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NVIC_SetPriority( ENET_IRQn, configMAC_INTERRUPT_PRIORITY );
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NVIC_EnableIRQ( ENET_IRQn );
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xReturn = pdPASS;
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}
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else
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{
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xReturn = pdFAIL;
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}
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configASSERT( xStatus != ERROR );
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return xReturn;
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}
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/*-----------------------------------------------------------*/
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portBASE_TYPE xNetworkInterfaceOutput( xNetworkBufferDescriptor_t * const pxNetworkBuffer )
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{
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portBASE_TYPE xReturn = pdFAIL;
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int32_t x;
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extern void EMAC_StartTransmitNextBuffer( uint32_t ulLength );
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extern void EMAC_SetNextPacketToSend( uint8_t * pucBuffer );
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/* Attempt to obtain access to a Tx buffer. */
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for( x = 0; x < niMAX_TX_ATTEMPTS; x++ )
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{
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if( EMAC_CheckTransmitIndex() == TRUE )
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{
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/* Will the data fit in the Tx buffer? */
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if( pxNetworkBuffer->xDataLength < EMAC_ETH_MAX_FLEN ) /*_RB_ The size needs to come from FreeRTOSIPConfig.h. */
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{
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/* Assign the buffer to the Tx descriptor that is now known to
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be free. */
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EMAC_SetNextPacketToSend( pxNetworkBuffer->pucBuffer );
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/* The EMAC now owns the buffer. */
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pxNetworkBuffer->pucBuffer = NULL;
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/* Initiate the Tx. */
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EMAC_StartTransmitNextBuffer( pxNetworkBuffer->xDataLength );
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iptraceNETWORK_INTERFACE_TRANSMIT();
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/* The Tx has been initiated. */
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xReturn = pdPASS;
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}
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break;
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}
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else
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{
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vTaskDelay( niTX_BUFFER_FREE_WAIT );
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}
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}
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/* Finished with the network buffer. */
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vNetworkBufferRelease( pxNetworkBuffer );
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return xReturn;
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}
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/*-----------------------------------------------------------*/
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void ENET_IRQHandler( void )
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{
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uint32_t ulInterruptCause;
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while( ( ulInterruptCause = LPC_EMAC->IntStatus ) != 0 )
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{
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/* Clear the interrupt. */
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LPC_EMAC->IntClear = ulInterruptCause;
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/* Clear fatal error conditions. NOTE: The driver does not clear all
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errors, only those actually experienced. For future reference, range
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errors are not actually errors so can be ignored. */
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if( ( ulInterruptCause & EMAC_INT_TX_UNDERRUN ) != 0U )
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{
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LPC_EMAC->Command |= EMAC_CR_TX_RES;
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}
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/* Unblock the deferred interrupt handler task if the event was an
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Rx. */
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if( ( ulInterruptCause & EMAC_INT_RX_DONE ) != 0UL )
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{
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xSemaphoreGiveFromISR( xEMACRxEventSemaphore, NULL );
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}
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}
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/* Shortcut calling portEND_SWITCHING_ISR(). */
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vPortYieldFromISR();
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}
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/*-----------------------------------------------------------*/
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static void prvEMACHandlerTask( void *pvParameters )
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{
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size_t xDataLength;
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const uint16_t usCRCLength = 4;
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xNetworkBufferDescriptor_t *pxNetworkBuffer;
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xIPStackEvent_t xRxEvent = { eEthernetRxEvent, NULL };
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/* This is not included in the header file for some reason. */
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extern uint8_t *EMAC_NextPacketToRead( void );
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( void ) pvParameters;
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configASSERT( xEMACRxEventSemaphore );
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for( ;; )
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{
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/* Wait for the EMAC interrupt to indicate that another packet has been
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received. The while() loop is only needed if INCLUDE_vTaskSuspend is
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set to 0 in FreeRTOSConfig.h. */
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while( xSemaphoreTake( xEMACRxEventSemaphore, portMAX_DELAY ) == pdFALSE );
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/* At least one packet has been received. */
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while( EMAC_CheckReceiveIndex() != FALSE )
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{
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/* Obtain the length, minus the CRC. The CRC is four bytes
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but the length is already minus 1. */
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xDataLength = ( size_t ) EMAC_GetReceiveDataSize() - ( usCRCLength - 1U );
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if( xDataLength > 0U )
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{
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/* Obtain a network buffer to pass this data into the
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stack. No storage is required as the network buffer
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will point directly to the buffer that already holds
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the received data. */
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pxNetworkBuffer = pxNetworkBufferGet( 0, ( portTickType ) 0 );
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if( pxNetworkBuffer != NULL )
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{
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pxNetworkBuffer->pucBuffer = EMAC_NextPacketToRead();
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pxNetworkBuffer->xDataLength = xDataLength;
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xRxEvent.pvData = ( void * ) pxNetworkBuffer;
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/* Data was received and stored. Send a message to the IP
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task to let it know. */
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if( xQueueSendToBack( xNetworkEventQueue, &xRxEvent, ( portTickType ) 0 ) == pdFALSE )
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{
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vNetworkBufferRelease( pxNetworkBuffer );
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iptraceETHERNET_RX_EVENT_LOST();
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}
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}
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else
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{
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iptraceETHERNET_RX_EVENT_LOST();
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}
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iptraceNETWORK_INTERFACE_RECEIVE();
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}
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/* Release the frame. */
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EMAC_UpdateRxConsumeIndex();
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}
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}
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}
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/*-----------------------------------------------------------*/
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,238 @@
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/***********************************************************************//**
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* @file lpc17xx_emac.h
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* @brief Contains all macro definitions and function prototypes
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* support for Ethernet MAC firmware library on LPC17xx
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* @version 2.0
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* @date 21. May. 2010
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* @author NXP MCU SW Application Team
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**************************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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**************************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @defgroup EMAC EMAC
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* @ingroup LPC1700CMSIS_FwLib_Drivers
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* @{
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*/
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#ifndef LPC18XX_EMAC_H_
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#define LPC18XX_EMAC_H_
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/* Includes ------------------------------------------------------------------- */
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#include "LPC18xx.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "lpc_types.h"
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/* Configuration */
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/* Interface Selection */
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#define MII 0 // =0 RMII - =1 MII
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/* End of Configuration */
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/* Descriptors Fields bits */
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#define OWN_BIT (1U<<31) /* Own bit in RDES0 & TDES0 */
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#define RX_END_RING (1<<15) /* Receive End of Ring bit in RDES1 */
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#define RX_NXTDESC_FLAG (1<<14) /* Second Address Chained bit in RDES1 */
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#define TX_LAST_SEGM (1<<29) /* Last Segment bit in TDES0 */
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#define RX_LAST_SEGM (1<<9)
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#define TX_FIRST_SEGM (1<<28) /* First Segment bit in TDES0 */
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#define RX_FIRST_SEGM (1<<8) /* First Segment bit in TDES0 */
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#define TX_END_RING (1<<21) /* Transmit End of Ring bit in TDES0 */
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#define TX_NXTDESC_FLAG (1<<20) /* Second Address Chained bit in TDES0 */
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/* EMAC Memory Buffer configuration for 16K Ethernet RAM */
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#define EMAC_ETH_MAX_FLEN ipETHERNET_FRAME_SIZE_TO_USE
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/* NOTE: EMAC_NUM_RX_FRAG is not used by the example FreeRTOS drivers - use
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configNUM_RX_ETHERNET_DMA_DESCRIPTORS. */
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#define EMAC_NUM_RX_FRAG 6 /**< Num.of RX Fragments */
|
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|
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/* NOTE: EMAC_NUM_TX_FRAG is not used by the example FreeRTOS drivers - use
|
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configNUM_TX_ETHERNET_DMA_DESCRIPTORS. */
|
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#define EMAC_NUM_TX_FRAG 2 /**< Num.of TX Fragments */
|
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|
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/* EMAC Control and Status bits */
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#define MAC_RX_ENABLE (1<<2) /* Receiver Enable in MAC_CONFIG reg */
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#define MAC_TX_ENABLE (1<<3) /* Transmitter Enable in MAC_CONFIG reg */
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#define MAC_PADCRC_STRIP (1<<7) /* Automatic Pad-CRC Stripping in MAC_CONFIG reg */
|
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#define MAC_DUPMODE (1<<11) /* Duplex Mode in MAC_CONFIG reg */
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#define MAC_100MPS (1<<14) /* Speed is 100Mbps in MAC_CONFIG reg */
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#define MAC_PROMISCUOUS (1U<<0) /* Promiscuous Mode bit in MAC_FRAME_FILTER reg */
|
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#define MAC_DIS_BROAD (1U<<5) /* Disable Broadcast Frames bit in MAC_FRAME_FILTER reg */
|
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#define MAC_RECEIVEALL (1U<<31) /* Receive All bit in MAC_FRAME_FILTER reg */
|
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#define DMA_SOFT_RESET 0x01 /* Software Reset bit in DMA_BUS_MODE reg */
|
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#define DMA_SS_RECEIVE (1<<1) /* Start/Stop Receive bit in DMA_OP_MODE reg */
|
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#define DMA_SS_TRANSMIT (1<<13) /* Start/Stop Transmission bit in DMA_OP_MODE reg */
|
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#define DMA_INT_TRANSMIT (1<<0) /* Transmit Interrupt Enable bit in DMA_INT_EN reg */
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#define DMA_INT_OVERFLOW (1<<4) /* Overflow Interrupt Enable bit in DMA_INT_EN reg */
|
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#define DMA_INT_UNDERFLW (1<<5) /* Underflow Interrupt Enable bit in DMA_INT_EN reg */
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#define DMA_INT_RECEIVE (1<<6) /* Receive Interrupt Enable bit in DMA_INT_EN reg */
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#define DMA_INT_ABN_SUM (1<<15) /* Abnormal Interrupt Summary Enable bit in DMA_INT_EN reg */
|
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#define DMA_INT_NOR_SUM (1<<16) /* Normal Interrupt Summary Enable bit in DMA_INT_EN reg */
|
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|
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/* MII Management Command Register */
|
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#define GMII_READ (0<<1) /* GMII Read PHY */
|
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#define GMII_WRITE (1<<1) /* GMII Write PHY */
|
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#define GMII_BUSY 0x00000001 /* GMII is Busy / Start Read/Write */
|
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#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
|
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#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
|
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|
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/* MII Management Address Register */
|
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#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
|
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|
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/* LAN8720 PHY Registers */
|
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#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
|
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#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
|
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#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
|
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#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
|
||||
#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
|
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#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
|
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#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
|
||||
#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
|
||||
|
||||
/* LAN8720 PHY Speed identify */
|
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#define PHY_REG_SPCON 0x1f /* Speed indication Register */
|
||||
#define PHY_REG_HCDSPEED_MASK 0x1c /* Speed indication Register mask*/
|
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#define PHY_REG_HCDSPEED_10MB_HALFD 0x04 /* Speed is 10Mbps HALF-duplex */
|
||||
#define PHY_REG_HCDSPEED_10MB_FULLD 0x14 /* Speed is 10Mbps FULL-duplex */
|
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#define PHY_REG_HCDSPEED_100MB_HALFD 0x08 /* Speed is 100Mbps HALF-duplex */
|
||||
#define PHY_REG_HCDSPEED_100MB_FULLD 0x18 /* Speed is 100Mbps FULL-duplex */
|
||||
|
||||
|
||||
/* PHY Extended Registers */
|
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#define PHY_REG_STS 0x10 /* Status Register */
|
||||
#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
|
||||
#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
|
||||
#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
|
||||
#define PHY_REG_RECR 0x15 /* Receive Error Counter */
|
||||
#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
|
||||
#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
|
||||
#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
|
||||
#define PHY_REG_PHYCR 0x19 /* PHY Control Register */
|
||||
#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
|
||||
#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
|
||||
#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
|
||||
|
||||
/* PHY Control and Status bits */
|
||||
#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
|
||||
#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
|
||||
#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
|
||||
#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
|
||||
#define PHY_AUTO_NEG 0x1000 /* Select Auto Negotiation */
|
||||
#define PHY_AUTO_NEG_DONE 0x0020 /* AutoNegotiation Complete in BMSR PHY reg */
|
||||
#define PHY_BMCR_RESET 0x8000 /* Reset bit at BMCR PHY reg */
|
||||
#define LINK_VALID_STS 0x0001 /* Link Valid Status at REG_STS PHY reg */
|
||||
#define FULL_DUP_STS 0x0004 /* Full Duplex Status at REG_STS PHY reg */
|
||||
#define SPEED_10M_STS 0x0002 /* 10Mbps Status at REG_STS PHY reg */
|
||||
|
||||
#define DP83848C_DEF_ADR 0x01 /* Default PHY device address */
|
||||
#define DP83848C_ID 0x20005C90 /* PHY Identifier (without Rev. info */
|
||||
#define LAN8720_ID 0x0007C0F1 /* PHY Identifier for SMSC PHY */
|
||||
|
||||
/* Misc */
|
||||
#define ETHERNET_RST 22 /* Reset Output for EMAC at RGU */
|
||||
#define RMII_SELECT 0x04 /* Select RMII in EMACCFG */
|
||||
|
||||
|
||||
/**
|
||||
* @brief EMAC configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
|
||||
- EMAC_MODE_AUTO
|
||||
- EMAC_MODE_10M_FULL
|
||||
- EMAC_MODE_10M_HALF
|
||||
- EMAC_MODE_100M_FULL
|
||||
- EMAC_MODE_100M_HALF
|
||||
*/
|
||||
uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
|
||||
of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
|
||||
*/
|
||||
} EMAC_CFG_Type;
|
||||
|
||||
/* Descriptor and status formats ---------------------------------------------- */
|
||||
/**
|
||||
* @brief RX Descriptor structure type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Status; /**< Receive Status Descriptor */
|
||||
uint32_t Ctrl; /**< Receive Control Descriptor */
|
||||
uint32_t Packet; /**< Receive Packet Descriptor */
|
||||
uint32_t NextDescripter;/**< Receive Next Descriptor Address */
|
||||
} RX_Desc;
|
||||
|
||||
/**
|
||||
* @brief RX Status structure type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Info; /**< Receive Information Status */
|
||||
uint32_t HashCRC; /**< Receive Hash CRC Status */
|
||||
} RX_Stat;
|
||||
|
||||
/**
|
||||
* @brief TX Descriptor structure type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Status; /**< Transmit Status Descriptor */
|
||||
uint32_t Ctrl; /**< Transmit Control Descriptor */
|
||||
uint32_t Packet; /**< Transmit Packet Descriptor */
|
||||
uint32_t NextDescripter; /**< Transmit Next Descriptor Address */
|
||||
} TX_Desc;
|
||||
|
||||
/**
|
||||
* @brief TX Status structure type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Info; /**< Transmit Information Status */
|
||||
} TX_Stat;
|
||||
|
||||
|
||||
/**
|
||||
* @brief TX Data Buffer structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t ulDataLen; /**< Data length */
|
||||
uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
|
||||
} EMAC_PACKETBUF_Type;
|
||||
|
||||
|
||||
|
||||
/* Prototypes */
|
||||
portBASE_TYPE EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
|
||||
int32_t EMAC_UpdatePHYStatus(void);
|
||||
uint32_t EMAC_GetReceiveDataSize(void);
|
||||
void EMAC_StartTransmitNextBuffer( uint32_t ulLength );
|
||||
void EMAC_SetNextPacketToSend( uint8_t * pucBuffer );
|
||||
void EMAC_NextPacketToRead( xNetworkBufferDescriptor_t *pxNetworkBuffer );
|
||||
void EMAC_UpdateRxConsumeIndex(void);
|
||||
portBASE_TYPE EMAC_CheckReceiveIndex(void);
|
||||
portBASE_TYPE EMAC_CheckTransmitIndex(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* LPC18XX_EMAC_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@ -0,0 +1,161 @@
|
||||
/*
|
||||
* FreeRTOS+UDP V1.0.0 (C) 2013 Real Time Engineers ltd.
|
||||
*
|
||||
* FreeRTOS+UDP is an add-on component to FreeRTOS. It is not, in itself, part
|
||||
* of the FreeRTOS kernel. FreeRTOS+UDP is licensed separately from FreeRTOS,
|
||||
* and uses a different license to FreeRTOS. FreeRTOS+UDP uses a dual license
|
||||
* model, information on which is provided below:
|
||||
*
|
||||
* - Open source licensing -
|
||||
* FreeRTOS+UDP is a free download and may be used, modified and distributed
|
||||
* without charge provided the user adheres to version two of the GNU General
|
||||
* Public license (GPL) and does not remove the copyright notice or this text.
|
||||
* The GPL V2 text is available on the gnu.org web site, and on the following
|
||||
* URL: http://www.FreeRTOS.org/gpl-2.0.txt
|
||||
*
|
||||
* - Commercial licensing -
|
||||
* Businesses and individuals who wish to incorporate FreeRTOS+UDP into
|
||||
* proprietary software for redistribution in any form must first obtain a
|
||||
* (very) low cost commercial license - and in-so-doing support the maintenance,
|
||||
* support and further development of the FreeRTOS+UDP product. Commercial
|
||||
* licenses can be obtained from http://shop.freertos.org and do not require any
|
||||
* source files to be changed.
|
||||
*
|
||||
* FreeRTOS+UDP is distributed in the hope that it will be useful. You cannot
|
||||
* use FreeRTOS+UDP unless you agree that you use the software 'as is'.
|
||||
* FreeRTOS+UDP is provided WITHOUT ANY WARRANTY; without even the implied
|
||||
* warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. Real Time Engineers Ltd. disclaims all conditions and terms, be they
|
||||
* implied, expressed, or statutory.
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://www.FreeRTOS.org/udp
|
||||
*
|
||||
*/
|
||||
|
||||
/* Standard includes. */
|
||||
#include <stdint.h>
|
||||
|
||||
/* FreeRTOS includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "queue.h"
|
||||
#include "semphr.h"
|
||||
|
||||
/* FreeRTOS+UDP includes. */
|
||||
#include "FreeRTOS_UDP_IP.h"
|
||||
#include "FreeRTOS_Sockets.h"
|
||||
#include "NetworkBufferManagement.h"
|
||||
|
||||
/* Hardware includes. */
|
||||
#include "hwEthernet.h"
|
||||
|
||||
/* Demo includes. */
|
||||
#include "NetworkInterface.h"
|
||||
|
||||
#if ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES != 1
|
||||
#define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eProcessBuffer
|
||||
#else
|
||||
#define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eConsiderFrameForProcessing( ( pucEthernetBuffer ) )
|
||||
#endif
|
||||
|
||||
/* When a packet is ready to be sent, if it cannot be sent immediately then the
|
||||
task performing the transmit will block for niTX_BUFFER_FREE_WAIT
|
||||
milliseconds. It will do this a maximum of niMAX_TX_ATTEMPTS before giving
|
||||
up. */
|
||||
#define niTX_BUFFER_FREE_WAIT ( ( portTickType ) 2UL / portTICK_RATE_MS )
|
||||
#define niMAX_TX_ATTEMPTS ( 5 )
|
||||
|
||||
/* The length of the queue used to send interrupt status words from the
|
||||
interrupt handler to the deferred handler task. */
|
||||
#define niINTERRUPT_QUEUE_LENGTH ( 10 )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* A deferred interrupt handler task that processes
|
||||
*/
|
||||
extern void vEMACHandlerTask( void *pvParameters );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The queue used to communicate Ethernet events with the IP task. */
|
||||
extern xQueueHandle xNetworkEventQueue;
|
||||
|
||||
/* The semaphore used to wake the deferred interrupt handler task when an Rx
|
||||
interrupt is received. */
|
||||
xSemaphoreHandle xEMACRxEventSemaphore = NULL;
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
portBASE_TYPE xNetworkInterfaceInitialise( void )
|
||||
{
|
||||
portBASE_TYPE xStatus, xReturn;
|
||||
extern uint8_t ucMACAddress[ 6 ];
|
||||
|
||||
/* Initialise the MAC. */
|
||||
vInitEmac();
|
||||
|
||||
while( lEMACWaitForLink() != pdPASS )
|
||||
{
|
||||
vTaskDelay( 20 );
|
||||
}
|
||||
|
||||
vSemaphoreCreateBinary( xEMACRxEventSemaphore );
|
||||
configASSERT( xEMACRxEventSemaphore );
|
||||
|
||||
/* The handler task is created at the highest possible priority to
|
||||
ensure the interrupt handler can return directly to it. */
|
||||
xTaskCreate( vEMACHandlerTask, ( const signed char * const ) "EMAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );
|
||||
xReturn = pdPASS;
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
portBASE_TYPE xNetworkInterfaceOutput( xNetworkBufferDescriptor_t * const pxNetworkBuffer )
|
||||
{
|
||||
extern void vEMACCopyWrite( uint8_t * pucBuffer, uint16_t usLength );
|
||||
|
||||
vEMACCopyWrite( pxNetworkBuffer->pucBuffer, pxNetworkBuffer->xDataLength );
|
||||
|
||||
/* Finished with the network buffer. */
|
||||
vNetworkBufferRelease( pxNetworkBuffer );
|
||||
|
||||
return pdTRUE;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if 0
|
||||
void ENET_IRQHandler( void )
|
||||
{
|
||||
uint32_t ulInterruptCause;
|
||||
|
||||
while( ( ulInterruptCause = LPC_EMAC->IntStatus ) != 0 )
|
||||
{
|
||||
/* Clear the interrupt. */
|
||||
LPC_EMAC->IntClear = ulInterruptCause;
|
||||
|
||||
/* Clear fatal error conditions. NOTE: The driver does not clear all
|
||||
errors, only those actually experienced. For future reference, range
|
||||
errors are not actually errors so can be ignored. */
|
||||
if( ( ulInterruptCause & EMAC_INT_TX_UNDERRUN ) != 0U )
|
||||
{
|
||||
LPC_EMAC->Command |= EMAC_CR_TX_RES;
|
||||
}
|
||||
|
||||
/* Unblock the deferred interrupt handler task if the event was an
|
||||
Rx. */
|
||||
if( ( ulInterruptCause & EMAC_INT_RX_DONE ) != 0UL )
|
||||
{
|
||||
xSemaphoreGiveFromISR( xEMACRxEventSemaphore, NULL );
|
||||
}
|
||||
}
|
||||
|
||||
/* Shortcut calling portEND_SWITCHING_ISR(). */
|
||||
vPortYieldFromISR();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user