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Use UBaseType_t as interrupt mask (#689)

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* Use UBaseType_t as interrupt mask
* Update GCC posix port to use UBaseType_t as interrupt mask
This commit is contained in:
chinglee-iot
2023-06-12 17:33:52 +08:00
committed by GitHub
parent 4a35c97fec
commit 80f67449ba
6 changed files with 51 additions and 51 deletions
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24
queue.c
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@ -1099,7 +1099,7 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
const BaseType_t xCopyPosition )
{
BaseType_t xReturn;
portBASE_TYPE xSavedInterruptStatus;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
configASSERT( pxQueue );
@ -1127,7 +1127,7 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
* read, instead return a flag to say whether a context switch is required or
* not (i.e. has a task with a higher priority than us been woken by this
* post). */
xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
{
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
{
@ -1252,7 +1252,7 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
xReturn = errQUEUE_FULL;
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus );
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
}
@ -1262,7 +1262,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
BaseType_t * const pxHigherPriorityTaskWoken )
{
BaseType_t xReturn;
portBASE_TYPE xSavedInterruptStatus;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
@ -1298,7 +1298,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
@ -1418,7 +1418,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
xReturn = errQUEUE_FULL;
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus );
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
}
@ -1933,7 +1933,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
BaseType_t * const pxHigherPriorityTaskWoken )
{
BaseType_t xReturn;
portBASE_TYPE xSavedInterruptStatus;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
configASSERT( pxQueue );
@ -1955,7 +1955,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
@ -2015,7 +2015,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus );
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
}
@ -2025,7 +2025,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
void * const pvBuffer )
{
BaseType_t xReturn;
portBASE_TYPE xSavedInterruptStatus;
UBaseType_t uxSavedInterruptStatus;
int8_t * pcOriginalReadPosition;
Queue_t * const pxQueue = xQueue;
@ -2049,7 +2049,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
{
/* Cannot block in an ISR, so check there is data available. */
if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
@ -2070,7 +2070,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus );
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
}