Rename directories in the RISC-V port.
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@ -61,14 +61,6 @@
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#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
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#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
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#define __FREERTOS_RISC_V_EXTENSIONS_H__
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#define __FREERTOS_RISC_V_EXTENSIONS_H__
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.macro portSAVE_ADDITIONAL_REGISTERS
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#define portasmHAS_CLINT 1
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/* This file is for use with chips that do not add to the standard RISC-V
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* register set, so there is nothing to do here. */
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.endm
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.macro portRESTORE_ADDITIONAL_REGISTERS
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/* This file is for use with chips that do not add to the standard RISC-V
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* register set, so there is nothing to do here. */
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.endm
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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@ -0,0 +1,73 @@
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/*
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* FreeRTOS Kernel V10.1.1
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* Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and t
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o permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
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*
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* + The code that is common to all RISC-V chips is implemented in
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
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* portASM.S file because the same file is used no matter which RISC-V chip is
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* in use.
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*
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* + The code that tailors the kernel's RISC-V port to a specific RISC-V
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* chip is implemented in freertos_risc_v_port_specific_extensions.h. There
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* is one freertos_risc_v_port_specific_extensions.h that can be used with any
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* RISC-V chip that both includes a standard CLINT and does not add to the
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* base set of RISC-V registers. There are additional
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* freertos_risc_v_port_specific_extensions.h files for RISC-V implementations
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* that do not include a standard CLINT or do add to the base set of RISC-V
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* regiters.
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*
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* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
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* freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP
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* IN USE. To include the correct freertos_risc_v_port_specific_extensions.h
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* header file ensure the path to the correct header file is in the assembler's
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* include path.
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*
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* This freertos_risc_v_port_specific_extensions.h is for use with Pulpino Ri5cy
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* devices, developed and tested using the Vega board RV32M1RM.
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*
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*/
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#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
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#define __FREERTOS_RISC_V_EXTENSIONS_H__
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#define portasmHAS_CLINT 0
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.macro portasmSAVE_ADDITIONAL_REGISTERS
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.endm
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.macro portasmRESTORE_ADDITIONAL_REGISTERS
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/* This file is for use with chips that do not add to the standard RISC-V
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* register set, so there is nothing to do here. */
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.endm
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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@ -206,11 +206,13 @@ const uint32_t ulMPIE_Bit = 0x80, ulMPP_Bits = 0x1800;
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}
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}
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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void vPortSetupTimerInterrupt( void )
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#if( configCLINT_BASE_ADDRESS != 0 )
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{
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uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
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void vPortSetupTimerInterrupt( void )
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volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFFC );
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{
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volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFF8 );
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uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
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volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFFC );
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volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFF8 );
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do
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do
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{
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{
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@ -226,7 +228,9 @@ volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCLI
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/* Prepare the time to use after the next tick interrupt. */
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/* Prepare the time to use after the next tick interrupt. */
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ullNextTime += ( uint64_t ) ulTimerIncrementsForOneTick;
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ullNextTime += ( uint64_t ) ulTimerIncrementsForOneTick;
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}
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}
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#endif /* ( configCLINT_BASE_ADDRESS != 0 ) */
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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BaseType_t xPortStartScheduler( void )
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@ -247,14 +251,26 @@ extern void xPortStartFirstTask( void );
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started. */
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started. */
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configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
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configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
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}
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}
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#endif
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#endif /* configASSERT_DEFINED */
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/* If there is a CLINT then it is ok to use the default implementation
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in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
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configure whichever clock is to be used to generate the tick interrupt. */
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vPortSetupTimerInterrupt();
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vPortSetupTimerInterrupt();
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#if( configCLINT_BASE_ADDRESS != 0 )
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{
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/* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11
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/* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11
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for external interrupt. _RB_ What happens here when mtime is not present as
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for external interrupt. _RB_ What happens here when mtime is not present as
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with pulpino? */
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with pulpino? */
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__asm volatile( "csrs mie, %0" :: "r"(0x880) );
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__asm volatile( "csrs mie, %0" :: "r"(0x880) );
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}
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#else
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{
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/* Enable external interrupts. */
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__asm volatile( "csrs mie, %0" :: "r"(0x800) );
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}
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#endif /* configCLINT_BASE_ADDRESS */
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xPortStartFirstTask();
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xPortStartFirstTask();
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