Fix MISRA C 2012 Rule 10.3 Violations (#974)
* Resolve violations for MISRA Rule 10.3-b2 * Formatting fix --------- Co-authored-by: bjbsmith <bjbsmith@uafeb6a6bcdce55.ant.amazon.com> Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
This commit is contained in:
8
queue.c
8
queue.c
@ -1190,7 +1190,7 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
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* read, instead return a flag to say whether a context switch is required or
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* not (i.e. has a task with a higher priority than us been woken by this
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* post). */
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uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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{
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if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
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{
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@ -1365,7 +1365,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
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* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
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uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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{
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const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
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@ -2055,7 +2055,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
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* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
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uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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{
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const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
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@ -2153,7 +2153,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
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* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
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uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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{
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/* Cannot block in an ISR, so check there is data available. */
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if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
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