283 lines
11 KiB
C
283 lines
11 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/* Kernel includes. */
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#include "FreeRTOS.h"
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/* Machine includes */
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#include <tc1782.h>
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#include <machine/intrinsics.h>
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#include <machine/cint.h>
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/*---------------------------------------------------------------------------*/
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/*
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* This reference is required by the Save/Restore Context Macros.
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*/
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extern volatile uint32_t * pxCurrentTCB;
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/*-----------------------------------------------------------*/
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/*
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* This file contains base definitions for all of the possible traps in the system.
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* It is suggested to provide implementations for all of the traps but for
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* the time being they simply trigger a DEBUG instruction so that it is easy
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* to see what caused a particular trap.
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*
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* Trap Class 6, the SYSCALL, is used exclusively by the operating system.
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*/
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/* The Trap Classes. */
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#define portMMU_TRAP 0
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#define portIPT_TRAP 1
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#define portIE_TRAP 2
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#define portCM_TRAP 3
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#define portSBP_TRAP 4
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#define portASSERT_TRAP 5
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#define portNMI_TRAP 7
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/* MMU Trap Identifications. */
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#define portTIN_MMU_VIRTUAL_ADDRESS_FILL 0
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#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION 1
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/* Internal Protection Trap Identifications. */
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#define portTIN_IPT_PRIVILEGED_INSTRUCTION 1
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#define portTIN_IPT_MEMORY_PROTECTION_READ 2
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#define portTIN_IPT_MEMORY_PROTECTION_WRITE 3
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#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION 4
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#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS 5
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#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS 6
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#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION 7
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/* Instruction Error Trap Identifications. */
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#define portTIN_IE_ILLEGAL_OPCODE 1
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#define portTIN_IE_UNIMPLEMENTED_OPCODE 2
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#define portTIN_IE_INVALID_OPERAND 3
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#define portTIN_IE_DATA_ADDRESS_ALIGNMENT 4
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#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS 5
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/* Context Management Trap Identifications. */
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#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION 1
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#define portTIN_CM_CALL_DEPTH_OVERFLOW 2
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#define portTIN_CM_CALL_DEPTH_UNDEFLOW 3
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#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW 4
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#define portTIN_CM_CALL_STACK_UNDERFLOW 5
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#define portTIN_CM_CONTEXT_TYPE 6
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#define portTIN_CM_NESTING_ERROR 7
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/* System Bus and Peripherals Trap Identifications. */
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#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR 1
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#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR 2
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#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR 3
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#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR 4
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#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR 5
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#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR 6
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/* Assertion Trap Identifications. */
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#define portTIN_ASSERT_ARITHMETIC_OVERFLOW 1
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#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW 2
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/* Non-maskable Interrupt Trap Identifications. */
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#define portTIN_NMI_NON_MASKABLE_INTERRUPT 0
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/*---------------------------------------------------------------------------*/
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void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
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void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
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void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
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void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
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void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
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void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
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void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
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/*---------------------------------------------------------------------------*/
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void vTrapInstallHandlers( void )
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{
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if( 0 == _install_trap_handler( portMMU_TRAP, vMMUTrap ) )
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{
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_debug();
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}
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if( 0 == _install_trap_handler( portIPT_TRAP, vInternalProtectionTrap ) )
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{
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_debug();
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}
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if( 0 == _install_trap_handler( portIE_TRAP, vInstructionErrorTrap ) )
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{
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_debug();
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}
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if( 0 == _install_trap_handler( portCM_TRAP, vContextManagementTrap ) )
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{
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_debug();
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}
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if( 0 == _install_trap_handler( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
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{
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_debug();
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}
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if( 0 == _install_trap_handler( portASSERT_TRAP, vAssertionTrap ) )
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{
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_debug();
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}
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if( 0 == _install_trap_handler( portNMI_TRAP, vNonMaskableInterruptTrap ) )
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{
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_debug();
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}
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}
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/*-----------------------------------------------------------*/
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void vMMUTrap( int iTrapIdentification )
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{
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switch( iTrapIdentification )
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{
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case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
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case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
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default:
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_debug();
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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void vInternalProtectionTrap( int iTrapIdentification )
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{
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/* Deliberate fall through to default. */
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switch( iTrapIdentification )
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{
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case portTIN_IPT_PRIVILEGED_INSTRUCTION:
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/* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
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case portTIN_IPT_MEMORY_PROTECTION_READ:
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/* Load word using invalid address. */
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case portTIN_IPT_MEMORY_PROTECTION_WRITE:
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/* Store Word using invalid address. */
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case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:
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/* PC jumped to an address outside of the valid range. */
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case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:
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/* Access to a peripheral denied at current execution level. */
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case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:
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/* NULL Pointer. */
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case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:
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/* Tried to modify a global address pointer register. */
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default:
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pxCurrentTCB[ 0 ] = __MFCR( $PCXI );
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_debug();
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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void vInstructionErrorTrap( int iTrapIdentification )
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{
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/* Deliberate fall through to default. */
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switch( iTrapIdentification )
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{
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case portTIN_IE_ILLEGAL_OPCODE:
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case portTIN_IE_UNIMPLEMENTED_OPCODE:
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case portTIN_IE_INVALID_OPERAND:
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case portTIN_IE_DATA_ADDRESS_ALIGNMENT:
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case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:
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default:
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_debug();
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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void vContextManagementTrap( int iTrapIdentification )
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{
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/* Deliberate fall through to default. */
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switch( iTrapIdentification )
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{
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case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:
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case portTIN_CM_CALL_DEPTH_OVERFLOW:
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case portTIN_CM_CALL_DEPTH_UNDEFLOW:
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case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:
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case portTIN_CM_CALL_STACK_UNDERFLOW:
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case portTIN_CM_CONTEXT_TYPE:
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case portTIN_CM_NESTING_ERROR:
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default:
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_debug();
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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void vSystemBusAndPeripheralsTrap( int iTrapIdentification )
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{
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/* Deliberate fall through to default. */
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switch( iTrapIdentification )
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{
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case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:
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case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:
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case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:
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case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:
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case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:
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case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:
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default:
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_debug();
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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void vAssertionTrap( int iTrapIdentification )
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{
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/* Deliberate fall through to default. */
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switch( iTrapIdentification )
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{
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case portTIN_ASSERT_ARITHMETIC_OVERFLOW:
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case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:
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default:
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_debug();
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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void vNonMaskableInterruptTrap( int iTrapIdentification )
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{
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/* Deliberate fall through to default. */
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switch( iTrapIdentification )
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{
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case portTIN_NMI_NON_MASKABLE_INTERRUPT:
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default:
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_debug();
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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