1492 lines
28 KiB
C
1492 lines
28 KiB
C
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#include <perfmon/perfmon_intel.h>
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static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
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{0x2F, 0x00, 0},
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};
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static perfmon_intel_pmc_event_t event_table[] = {
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{
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.event_code = {0x14},
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.umask = 0x1,
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.event_name = "arith.cycles_div_busy",
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},
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{
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.event_code = {0x14},
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.umask = 0x1,
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.event_name = "arith.div",
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},
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{
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.event_code = {0x14},
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.umask = 0x2,
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.event_name = "arith.mul",
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},
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{
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.event_code = {0xE6},
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.umask = 0x2,
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.event_name = "baclear.bad_target",
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},
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{
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.event_code = {0xE6},
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.umask = 0x1,
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.event_name = "baclear.clear",
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},
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{
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.event_code = {0xA7},
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.umask = 0x1,
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.event_name = "baclear_force_iq",
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},
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{
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.event_code = {0xE8},
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.umask = 0x1,
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.event_name = "bpu_clears.early",
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},
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{
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.event_code = {0xE8},
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.umask = 0x2,
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.event_name = "bpu_clears.late",
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},
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{
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.event_code = {0xE5},
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.umask = 0x1,
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.event_name = "bpu_missed_call_ret",
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},
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{
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.event_code = {0xE0},
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.umask = 0x1,
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.event_name = "br_inst_decoded",
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},
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{
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.event_code = {0x88},
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.umask = 0x7F,
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.event_name = "br_inst_exec.any",
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},
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{
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.event_code = {0x88},
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.umask = 0x1,
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.event_name = "br_inst_exec.cond",
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},
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{
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.event_code = {0x88},
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.umask = 0x2,
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.event_name = "br_inst_exec.direct",
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},
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{
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.event_code = {0x88},
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.umask = 0x10,
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.event_name = "br_inst_exec.direct_near_call",
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},
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{
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.event_code = {0x88},
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.umask = 0x20,
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.event_name = "br_inst_exec.indirect_near_call",
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},
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{
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.event_code = {0x88},
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.umask = 0x4,
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.event_name = "br_inst_exec.indirect_non_call",
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},
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{
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.event_code = {0x88},
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.umask = 0x30,
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.event_name = "br_inst_exec.near_calls",
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},
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{
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.event_code = {0x88},
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.umask = 0x7,
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.event_name = "br_inst_exec.non_calls",
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},
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{
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.event_code = {0x88},
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.umask = 0x8,
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.event_name = "br_inst_exec.return_near",
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},
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{
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.event_code = {0x88},
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.umask = 0x40,
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.event_name = "br_inst_exec.taken",
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},
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{
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.event_code = {0xC4},
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.umask = 0x4,
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.event_name = "br_inst_retired.all_branches",
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},
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{
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.event_code = {0xC4},
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.umask = 0x1,
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.event_name = "br_inst_retired.conditional",
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},
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{
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.event_code = {0xC4},
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.umask = 0x2,
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.event_name = "br_inst_retired.near_call",
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},
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{
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.event_code = {0x89},
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.umask = 0x7F,
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.event_name = "br_misp_exec.any",
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},
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{
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.event_code = {0x89},
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.umask = 0x1,
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.event_name = "br_misp_exec.cond",
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},
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{
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.event_code = {0x89},
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.umask = 0x2,
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.event_name = "br_misp_exec.direct",
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},
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{
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.event_code = {0x89},
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.umask = 0x10,
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.event_name = "br_misp_exec.direct_near_call",
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},
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{
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.event_code = {0x89},
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.umask = 0x20,
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.event_name = "br_misp_exec.indirect_near_call",
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},
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{
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.event_code = {0x89},
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.umask = 0x4,
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.event_name = "br_misp_exec.indirect_non_call",
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},
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{
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.event_code = {0x89},
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.umask = 0x30,
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.event_name = "br_misp_exec.near_calls",
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},
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{
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.event_code = {0x89},
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.umask = 0x7,
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.event_name = "br_misp_exec.non_calls",
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},
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{
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.event_code = {0x89},
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.umask = 0x8,
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.event_name = "br_misp_exec.return_near",
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},
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{
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.event_code = {0x89},
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.umask = 0x40,
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.event_name = "br_misp_exec.taken",
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},
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{
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.event_code = {0xC5},
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.umask = 0x4,
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.event_name = "br_misp_retired.all_branches",
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},
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{
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.event_code = {0xC5},
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.umask = 0x1,
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.event_name = "br_misp_retired.conditional",
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},
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{
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.event_code = {0xC5},
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.umask = 0x2,
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.event_name = "br_misp_retired.near_call",
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},
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{
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.event_code = {0x63},
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.umask = 0x2,
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.event_name = "cache_lock_cycles.l1d",
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},
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{
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.event_code = {0x63},
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.umask = 0x1,
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.event_name = "cache_lock_cycles.l1d_l2",
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},
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{
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.event_code = {0x0},
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.umask = 0x0,
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.event_name = "cpu_clk_unhalted.ref",
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},
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{
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.event_code = {0x3C},
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.umask = 0x1,
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.event_name = "cpu_clk_unhalted.ref_p",
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},
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{
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.event_code = {0x0},
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.umask = 0x0,
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.event_name = "cpu_clk_unhalted.thread",
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},
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{
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.event_code = {0x3C},
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.umask = 0x0,
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.event_name = "cpu_clk_unhalted.thread_p",
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},
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{
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.event_code = {0x3C},
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.umask = 0x0,
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.event_name = "cpu_clk_unhalted.total_cycles",
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},
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{
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.event_code = {0x8},
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.umask = 0x1,
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.event_name = "dtlb_load_misses.any",
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},
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{
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.event_code = {0x8},
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.umask = 0x80,
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.event_name = "dtlb_load_misses.large_walk_completed",
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},
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{
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.event_code = {0x8},
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.umask = 0x20,
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.event_name = "dtlb_load_misses.pde_miss",
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},
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{
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.event_code = {0x8},
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.umask = 0x10,
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.event_name = "dtlb_load_misses.stlb_hit",
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},
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{
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.event_code = {0x8},
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.umask = 0x2,
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.event_name = "dtlb_load_misses.walk_completed",
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},
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{
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.event_code = {0x8},
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.umask = 0x4,
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.event_name = "dtlb_load_misses.walk_cycles",
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},
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{
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.event_code = {0x49},
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.umask = 0x1,
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.event_name = "dtlb_misses.any",
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},
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{
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.event_code = {0x49},
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.umask = 0x80,
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.event_name = "dtlb_misses.large_walk_completed",
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},
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{
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.event_code = {0x49},
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.umask = 0x20,
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.event_name = "dtlb_misses.pde_miss",
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},
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{
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.event_code = {0x49},
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.umask = 0x10,
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.event_name = "dtlb_misses.stlb_hit",
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},
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{
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.event_code = {0x49},
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.umask = 0x2,
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.event_name = "dtlb_misses.walk_completed",
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},
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{
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.event_code = {0x49},
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.umask = 0x4,
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.event_name = "dtlb_misses.walk_cycles",
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},
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{
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.event_code = {0x4F},
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.umask = 0x10,
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.event_name = "ept.walk_cycles",
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},
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{
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.event_code = {0xD5},
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.umask = 0x1,
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.event_name = "es_reg_renames",
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},
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{
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.event_code = {0xF7},
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.umask = 0x1,
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.event_name = "fp_assist.all",
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},
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{
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.event_code = {0xF7},
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.umask = 0x4,
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.event_name = "fp_assist.input",
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},
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{
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.event_code = {0xF7},
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.umask = 0x2,
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.event_name = "fp_assist.output",
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},
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{
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.event_code = {0x10},
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.umask = 0x2,
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.event_name = "fp_comp_ops_exe.mmx",
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},
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{
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.event_code = {0x10},
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.umask = 0x80,
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.event_name = "fp_comp_ops_exe.sse_double_precision",
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},
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{
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.event_code = {0x10},
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.umask = 0x4,
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.event_name = "fp_comp_ops_exe.sse_fp",
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},
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{
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.event_code = {0x10},
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.umask = 0x10,
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.event_name = "fp_comp_ops_exe.sse_fp_packed",
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},
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{
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.event_code = {0x10},
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.umask = 0x20,
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.event_name = "fp_comp_ops_exe.sse_fp_scalar",
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},
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{
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.event_code = {0x10},
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.umask = 0x40,
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.event_name = "fp_comp_ops_exe.sse_single_precision",
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},
|
||
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{
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||
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.event_code = {0x10},
|
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.umask = 0x8,
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.event_name = "fp_comp_ops_exe.sse2_integer",
|
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},
|
||
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{
|
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.event_code = {0x10},
|
||
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.umask = 0x1,
|
||
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.event_name = "fp_comp_ops_exe.x87",
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||
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},
|
||
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{
|
||
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.event_code = {0xCC},
|
||
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.umask = 0x3,
|
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.event_name = "fp_mmx_trans.any",
|
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},
|
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{
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||
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.event_code = {0xCC},
|
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.umask = 0x1,
|
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.event_name = "fp_mmx_trans.to_fp",
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},
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{
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.event_code = {0xCC},
|
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.umask = 0x2,
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.event_name = "fp_mmx_trans.to_mmx",
|
||
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},
|
||
|
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{
|
||
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.event_code = {0x87},
|
||
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.umask = 0xF,
|
||
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.event_name = "ild_stall.any",
|
||
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|
},
|
||
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{
|
||
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.event_code = {0x87},
|
||
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.umask = 0x4,
|
||
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.event_name = "ild_stall.iq_full",
|
||
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},
|
||
|
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{
|
||
|
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.event_code = {0x87},
|
||
|
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.umask = 0x1,
|
||
|
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.event_name = "ild_stall.lcp",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x87},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "ild_stall.mru",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x87},
|
||
|
|
.umask = 0x8,
|
||
|
|
.event_name = "ild_stall.regen",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x18},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "inst_decoded.dec0",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x1E},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "inst_queue_write_cycles",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x17},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "inst_queue_writes",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
.umask = 0x1,
|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xC0},
|
||
|
|
.umask = 0x4,
|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xC0},
|
||
|
|
.umask = 0x1,
|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xC0},
|
||
|
|
.umask = 0x2,
|
||
|
|
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|
||
|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x6C},
|
||
|
|
.umask = 0x1,
|
||
|
|
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|
||
|
|
},
|
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|
|
{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
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},
|
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|
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{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
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},
|
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{
|
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|
|
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|
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|
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|
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|
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|
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|
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|
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{
|
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|
|
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|
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|
|
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|
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|
|
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|
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|
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},
|
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|
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{
|
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|
|
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|
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|
|
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|
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|
|
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|
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|
|
},
|
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|
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{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x51},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "l1d.m_evict",
|
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|
|
},
|
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|
|
{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x51},
|
||
|
|
.umask = 0x8,
|
||
|
|
.event_name = "l1d.m_snoop_evict",
|
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|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x51},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "l1d.repl",
|
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|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x52},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "l1d_cache_prefetch_lock_fb_hit",
|
||
|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x4E},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "l1d_prefetch.miss",
|
||
|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x4E},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "l1d_prefetch.requests",
|
||
|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x4E},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "l1d_prefetch.triggers",
|
||
|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x28},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "l1d_wb_l2.e_state",
|
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|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x28},
|
||
|
|
.umask = 0x1,
|
||
|
|
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|
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|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x28},
|
||
|
|
.umask = 0x8,
|
||
|
|
.event_name = "l1d_wb_l2.m_state",
|
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|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x28},
|
||
|
|
.umask = 0xF,
|
||
|
|
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|
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|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x28},
|
||
|
|
.umask = 0x2,
|
||
|
|
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|
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|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x80},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "l1i.cycles_stalled",
|
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|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x80},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "l1i.hits",
|
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|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0x80},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "l1i.misses",
|
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|
|
},
|
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|
|
{
|
||
|
|
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|
||
|
|
.umask = 0x3,
|
||
|
|
.event_name = "l1i.reads",
|
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|
|
},
|
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|
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{
|
||
|
|
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|
||
|
|
.umask = 0xFF,
|
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|
|
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|
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|
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},
|
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|
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{
|
||
|
|
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|
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|
|
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|
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|
|
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|
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|
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},
|
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|
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{
|
||
|
|
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|
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|
|
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|
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|
|
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|
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|
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},
|
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{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
|
},
|
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|
|
{
|
||
|
|
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|
||
|
|
.umask = 0xF,
|
||
|
|
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|
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|
|
},
|
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|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
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|
|
},
|
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|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
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|
|
},
|
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|
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{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
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|
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|
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{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
|
},
|
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|
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{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
|
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|
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|
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{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
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|
|
},
|
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|
|
{
|
||
|
|
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|
||
|
|
.umask = 0x7,
|
||
|
|
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|
||
|
|
},
|
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|
|
{
|
||
|
|
.event_code = {0xF1},
|
||
|
|
.umask = 0x4,
|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xF1},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "l2_lines_in.s_state",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xF2},
|
||
|
|
.umask = 0xF,
|
||
|
|
.event_name = "l2_lines_out.any",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xF2},
|
||
|
|
.umask = 0x1,
|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
.umask = 0x4,
|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
.umask = 0x8,
|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
.umask = 0x10,
|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
.umask = 0x20,
|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
.umask = 0x30,
|
||
|
|
.event_name = "l2_rqsts.ifetches",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "l2_rqsts.ld_hit",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
.umask = 0x2,
|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x24},
|
||
|
|
.umask = 0x3,
|
||
|
|
.event_name = "l2_rqsts.loads",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
.umask = 0xAA,
|
||
|
|
.event_name = "l2_rqsts.miss",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x24},
|
||
|
|
.umask = 0x40,
|
||
|
|
.event_name = "l2_rqsts.prefetch_hit",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x24},
|
||
|
|
.umask = 0x80,
|
||
|
|
.event_name = "l2_rqsts.prefetch_miss",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x24},
|
||
|
|
.umask = 0xC0,
|
||
|
|
.event_name = "l2_rqsts.prefetches",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x24},
|
||
|
|
.umask = 0xFF,
|
||
|
|
.event_name = "l2_rqsts.references",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "l2_rqsts.rfo_hit",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x24},
|
||
|
|
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|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x24},
|
||
|
|
.umask = 0xC,
|
||
|
|
.event_name = "l2_rqsts.rfos",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xF0},
|
||
|
|
.umask = 0x80,
|
||
|
|
.event_name = "l2_transactions.any",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xF0},
|
||
|
|
.umask = 0x20,
|
||
|
|
.event_name = "l2_transactions.fill",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xF0},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "l2_transactions.ifetch",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xF0},
|
||
|
|
.umask = 0x10,
|
||
|
|
.event_name = "l2_transactions.l1d_wb",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xF0},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "l2_transactions.load",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xF0},
|
||
|
|
.umask = 0x8,
|
||
|
|
.event_name = "l2_transactions.prefetch",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xF0},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "l2_transactions.rfo",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xF0},
|
||
|
|
.umask = 0x40,
|
||
|
|
.event_name = "l2_transactions.wb",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x27},
|
||
|
|
.umask = 0x40,
|
||
|
|
.event_name = "l2_write.lock.e_state",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x27},
|
||
|
|
.umask = 0xE0,
|
||
|
|
.event_name = "l2_write.lock.hit",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x27},
|
||
|
|
.umask = 0x10,
|
||
|
|
.event_name = "l2_write.lock.i_state",
|
||
|
|
},
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
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|
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{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
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|
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{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
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|
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{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
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|
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{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
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|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
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|
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|
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|
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{
|
||
|
|
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|
||
|
|
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|
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|
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|
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|
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|
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{
|
||
|
|
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|
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|
|
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|
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|
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|
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|
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|
|
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|
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|
|
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|
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|
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|
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|
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|
|
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|
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|
|
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|
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|
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|
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|
|
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|
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|
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|
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|
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|
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|
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{
|
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|
|
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|
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|
|
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|
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|
|
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|
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|
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{
|
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|
|
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|
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|
|
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|
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|
|
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|
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|
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|
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|
|
{
|
||
|
|
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|
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|
|
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|
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|
|
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|
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|
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|
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{
|
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|
|
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|
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|
|
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|
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|
|
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|
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|
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|
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{
|
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|
|
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|
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|
|
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|
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|
|
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|
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|
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|
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|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
|
{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
|
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|
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|
|
{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
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|
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|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
.event_name = "machine_clears.mem_order",
|
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|
|
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|
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|
|
{
|
||
|
|
.event_code = {0xC3},
|
||
|
|
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|
||
|
|
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|
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|
|
},
|
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|
|
{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
|
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|
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|
|
{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
|
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|
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|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
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{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
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|
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|
|
{
|
||
|
|
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|
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|
|
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|
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|
|
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|
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|
|
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|
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|
|
{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
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|
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|
|
{
|
||
|
|
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|
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|
|
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|
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|
|
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|
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|
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|
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|
{
|
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|
|
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|
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|
|
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|
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|
|
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|
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|
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|
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{
|
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|
|
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|
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|
|
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|
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|
|
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|
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|
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|
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|
|
{
|
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|
|
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|
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|
|
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|
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|
|
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|
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|
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},
|
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|
|
{
|
||
|
|
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|
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|
|
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|
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|
|
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|
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{
|
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|
|
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|
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|
|
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|
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|
|
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|
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|
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|
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|
|
{
|
||
|
|
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|
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|
|
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|
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|
|
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|
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|
|
},
|
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|
|
{
|
||
|
|
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|
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|
|
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|
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|
|
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|
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|
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|
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|
|
{
|
||
|
|
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|
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|
|
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|
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|
|
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|
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|
|
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|
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|
{
|
||
|
|
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|
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|
|
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|
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|
|
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|
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|
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},
|
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{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
|
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|
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{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
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|
|
},
|
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|
|
{
|
||
|
|
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|
||
|
|
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|
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|
|
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|
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|
|
},
|
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|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
.umask = 0x2,
|
||
|
|
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|
||
|
|
},
|
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|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
},
|
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|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
.umask = 0x40,
|
||
|
|
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|
||
|
|
},
|
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|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
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|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
.event_name = "offcore_requests_outstanding.demand.rfo",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB2},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "offcore_requests_sq_full",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x7},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "partial_address_alias",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
.umask = 0xF,
|
||
|
|
.event_name = "rat_stalls.any",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
.event_name = "rat_stalls.flags",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "rat_stalls.registers",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
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|
||
|
|
.event_name = "rat_stalls.rob_read_port",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
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|
||
|
|
.umask = 0x8,
|
||
|
|
.event_name = "rat_stalls.scoreboard",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xA2},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "resource_stalls.any",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xA2},
|
||
|
|
.umask = 0x20,
|
||
|
|
.event_name = "resource_stalls.fpcw",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xA2},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "resource_stalls.load",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xA2},
|
||
|
|
.umask = 0x40,
|
||
|
|
.event_name = "resource_stalls.mxcsr",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xA2},
|
||
|
|
.umask = 0x80,
|
||
|
|
.event_name = "resource_stalls.other",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xA2},
|
||
|
|
.umask = 0x10,
|
||
|
|
.event_name = "resource_stalls.rob_full",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xA2},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "resource_stalls.rs_full",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xA2},
|
||
|
|
.umask = 0x8,
|
||
|
|
.event_name = "resource_stalls.store",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x4},
|
||
|
|
.umask = 0x7,
|
||
|
|
.event_name = "sb_drain.any",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xD4},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "seg_rename_stalls",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x12},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "simd_int_128.pack",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x12},
|
||
|
|
.umask = 0x20,
|
||
|
|
.event_name = "simd_int_128.packed_arith",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x12},
|
||
|
|
.umask = 0x10,
|
||
|
|
.event_name = "simd_int_128.packed_logical",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x12},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "simd_int_128.packed_mpy",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x12},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "simd_int_128.packed_shift",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x12},
|
||
|
|
.umask = 0x40,
|
||
|
|
.event_name = "simd_int_128.shuffle_move",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x12},
|
||
|
|
.umask = 0x8,
|
||
|
|
.event_name = "simd_int_128.unpack",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xFD},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "simd_int_64.pack",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xFD},
|
||
|
|
.umask = 0x20,
|
||
|
|
.event_name = "simd_int_64.packed_arith",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xFD},
|
||
|
|
.umask = 0x10,
|
||
|
|
.event_name = "simd_int_64.packed_logical",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xFD},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "simd_int_64.packed_mpy",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xFD},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "simd_int_64.packed_shift",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xFD},
|
||
|
|
.umask = 0x40,
|
||
|
|
.event_name = "simd_int_64.shuffle_move",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xFD},
|
||
|
|
.umask = 0x8,
|
||
|
|
.event_name = "simd_int_64.unpack",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB8},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "snoop_response.hit",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB8},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "snoop_response.hite",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB8},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "snoop_response.hitm",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB4},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "snoopq_requests.code",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB4},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "snoopq_requests.data",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB4},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "snoopq_requests.invalidate",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB3},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "snoopq_requests_outstanding.code",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB3},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "snoopq_requests_outstanding.code_not_empty",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB3},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "snoopq_requests_outstanding.data",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB3},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "snoopq_requests_outstanding.data_not_empty",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB3},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "snoopq_requests_outstanding.invalidate",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB3},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "snoopq_requests_outstanding.invalidate_not_empty",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xF6},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "sq_full_stall_cycles",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xF4},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "sq_misc.lru_hints",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xF4},
|
||
|
|
.umask = 0x10,
|
||
|
|
.event_name = "sq_misc.split_lock",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xC7},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "ssex_uops_retired.packed_double",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xC7},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "ssex_uops_retired.packed_single",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xC7},
|
||
|
|
.umask = 0x8,
|
||
|
|
.event_name = "ssex_uops_retired.scalar_double",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xC7},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "ssex_uops_retired.scalar_single",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xC7},
|
||
|
|
.umask = 0x10,
|
||
|
|
.event_name = "ssex_uops_retired.vector_integer",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x6},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "store_blocks.at_ret",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x6},
|
||
|
|
.umask = 0x8,
|
||
|
|
.event_name = "store_blocks.l1d_block",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x3C},
|
||
|
|
.umask = 0x0,
|
||
|
|
.event_name = "cpu_clk_unhalted.thread_p",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0x19},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "two_uop_insts_decoded",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xDB},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "uop_unfusion",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xD1},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "uops_decoded.esp_folding",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xD1},
|
||
|
|
.umask = 0x8,
|
||
|
|
.event_name = "uops_decoded.esp_sync",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xD1},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "uops_decoded.ms_cycles_active",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xD1},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "uops_decoded.stall_cycles",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB1},
|
||
|
|
.umask = 0x3F,
|
||
|
|
.event_name = "uops_executed.core_active_cycles",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB1},
|
||
|
|
.umask = 0x1F,
|
||
|
|
.event_name = "uops_executed.core_active_cycles_no_port5",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB1},
|
||
|
|
.umask = 0x3F,
|
||
|
|
.event_name = "uops_executed.core_stall_count",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB1},
|
||
|
|
.umask = 0x1F,
|
||
|
|
.event_name = "uops_executed.core_stall_count_no_port5",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB1},
|
||
|
|
.umask = 0x3F,
|
||
|
|
.event_name = "uops_executed.core_stall_cycles",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB1},
|
||
|
|
.umask = 0x1F,
|
||
|
|
.event_name = "uops_executed.core_stall_cycles_no_port5",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB1},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "uops_executed.port0",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB1},
|
||
|
|
.umask = 0x40,
|
||
|
|
.event_name = "uops_executed.port015",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB1},
|
||
|
|
.umask = 0x40,
|
||
|
|
.event_name = "uops_executed.port015_stall_cycles",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB1},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "uops_executed.port1",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB1},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "uops_executed.port2_core",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB1},
|
||
|
|
.umask = 0x80,
|
||
|
|
.event_name = "uops_executed.port234_core",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB1},
|
||
|
|
.umask = 0x8,
|
||
|
|
.event_name = "uops_executed.port3_core",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB1},
|
||
|
|
.umask = 0x10,
|
||
|
|
.event_name = "uops_executed.port4_core",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xB1},
|
||
|
|
.umask = 0x20,
|
||
|
|
.event_name = "uops_executed.port5",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xE},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "uops_issued.any",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xE},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "uops_issued.core_stall_cycles",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xE},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "uops_issued.cycles_all_threads",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xE},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "uops_issued.fused",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xE},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "uops_issued.stall_cycles",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xC2},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "uops_retired.active_cycles",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xC2},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "uops_retired.any",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xC2},
|
||
|
|
.umask = 0x4,
|
||
|
|
.event_name = "uops_retired.macro_fused",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xC2},
|
||
|
|
.umask = 0x2,
|
||
|
|
.event_name = "uops_retired.retire_slots",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xC2},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "uops_retired.stall_cycles",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xC2},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "uops_retired.total_cycles",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_code = {0xC0},
|
||
|
|
.umask = 0x1,
|
||
|
|
.event_name = "inst_retired.total_cycles_ps",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.event_name = 0,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
|
||
|
|
|