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dma_intel: fix potential invalid batch status

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DMA batch status was set by hardware. Its value may be variable between
cpus twice accesses. Saving the value of status can fix it.

Type: fix

Signed-off-by: Marvin Liu <yong.liu@intel.com>
Change-Id: Ibc9337239555744a571685b486c986991c3e9b18
This commit is contained in:
Marvin Liu
2023-03-15 23:00:52 +08:00
parent f4ddf16eec
commit 6a6df00abc
1 changed files with 6 additions and 5 deletions
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11
src/plugins/dma_intel/dsa.c
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@ -350,7 +350,7 @@ intel_dsa_node_fn (vlib_main_t *vm, vlib_node_runtime_t *node,
intel_dsa_thread_t *t = intel_dsa_thread_t *t =
vec_elt_at_index (idm->dsa_threads, vm->thread_index); vec_elt_at_index (idm->dsa_threads, vm->thread_index);
u32 n_pending = 0, n = 0; u32 n_pending = 0, n = 0;
u8 glitch = 0; u8 glitch = 0, status;
if (!t->pending_batches) if (!t->pending_batches)
return 0; return 0;
@ -362,8 +362,9 @@ intel_dsa_node_fn (vlib_main_t *vm, vlib_node_runtime_t *node,
intel_dsa_batch_t *b = t->pending_batches[i]; intel_dsa_batch_t *b = t->pending_batches[i];
intel_dsa_channel_t *ch = b->ch; intel_dsa_channel_t *ch = b->ch;
if ((b->status == INTEL_DSA_STATUS_SUCCESS || status = b->status;
b->status == INTEL_DSA_STATUS_CPU_SUCCESS) && if ((status == INTEL_DSA_STATUS_SUCCESS ||
status == INTEL_DSA_STATUS_CPU_SUCCESS) &&
!glitch) !glitch)
{ {
/* callback */ /* callback */
@ -384,7 +385,7 @@ intel_dsa_node_fn (vlib_main_t *vm, vlib_node_runtime_t *node,
vec_add1 (idm->dsa_config_heap[b->config_heap_index].freelist, b); vec_add1 (idm->dsa_config_heap[b->config_heap_index].freelist, b);
intel_dsa_channel_lock (ch); intel_dsa_channel_lock (ch);
if (b->status == INTEL_DSA_STATUS_SUCCESS) if (status == INTEL_DSA_STATUS_SUCCESS)
{ {
ch->n_enq--; ch->n_enq--;
ch->completed++; ch->completed++;
@ -396,7 +397,7 @@ intel_dsa_node_fn (vlib_main_t *vm, vlib_node_runtime_t *node,
b->batch.n_enq = 0; b->batch.n_enq = 0;
b->status = INTEL_DSA_STATUS_IDLE; b->status = INTEL_DSA_STATUS_IDLE;
} }
else if (b->status == INTEL_DSA_STATUS_BUSY) else if (status == INTEL_DSA_STATUS_BUSY)
{ {
glitch = 1 & b->barrier_before_last; glitch = 1 & b->barrier_before_last;
t->pending_batches[n++] = b; t->pending_batches[n++] = b;