7f83738b46
0001 ~ 0014 patches are for virtual channel and PMD 0015 is the iavf fdir framework 0016 ~ 0017 are for the iavf fidr driver Type: feature Signed-off-by: Chenmin Sun <chenmin.sun@intel.com> Change-Id: I38e69ca0065a71cc6ba0b44ef7c7db51193a0899
227 lines
5.8 KiB
Diff
227 lines
5.8 KiB
Diff
From a7cbf4fabd46b0d02b651f5defac754e56e11e0e Mon Sep 17 00:00:00 2001
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From: Leyi Rong <leyi.rong@intel.com>
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Date: Wed, 8 Apr 2020 14:22:00 +0800
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Subject: [DPDK 07/17] net/iavf: flexible Rx descriptor definitions
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Add definitions for flexible Rx descriptor structures and macros.
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Signed-off-by: Leyi Rong <leyi.rong@intel.com>
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---
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drivers/net/iavf/iavf_rxtx.h | 200 +++++++++++++++++++++++++++++++++++
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1 file changed, 200 insertions(+)
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diff --git a/drivers/net/iavf/iavf_rxtx.h b/drivers/net/iavf/iavf_rxtx.h
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index 09b5bd99e..5e309631e 100644
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--- a/drivers/net/iavf/iavf_rxtx.h
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+++ b/drivers/net/iavf/iavf_rxtx.h
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@@ -157,6 +157,206 @@ union iavf_tx_offload {
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};
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};
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+/* Rx Flex Descriptors
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+ * These descriptors are used instead of the legacy version descriptors
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+ */
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+union iavf_16b_rx_flex_desc {
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+ struct {
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+ __le64 pkt_addr; /* Packet buffer address */
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+ __le64 hdr_addr; /* Header buffer address */
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+ /* bit 0 of hdr_addr is DD bit */
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+ } read;
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+ struct {
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+ /* Qword 0 */
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+ u8 rxdid; /* descriptor builder profile ID */
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+ u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
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+ __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
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+ __le16 pkt_len; /* [15:14] are reserved */
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+ __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
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+ /* sph=[11:11] */
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+ /* ff1/ext=[15:12] */
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+
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+ /* Qword 1 */
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+ __le16 status_error0;
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+ __le16 l2tag1;
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+ __le16 flex_meta0;
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+ __le16 flex_meta1;
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+ } wb; /* writeback */
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+};
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+
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+union iavf_32b_rx_flex_desc {
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+ struct {
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+ __le64 pkt_addr; /* Packet buffer address */
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+ __le64 hdr_addr; /* Header buffer address */
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+ /* bit 0 of hdr_addr is DD bit */
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+ __le64 rsvd1;
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+ __le64 rsvd2;
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+ } read;
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+ struct {
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+ /* Qword 0 */
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+ u8 rxdid; /* descriptor builder profile ID */
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+ u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
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+ __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
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+ __le16 pkt_len; /* [15:14] are reserved */
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+ __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
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+ /* sph=[11:11] */
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+ /* ff1/ext=[15:12] */
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+
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+ /* Qword 1 */
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+ __le16 status_error0;
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+ __le16 l2tag1;
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+ __le16 flex_meta0;
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+ __le16 flex_meta1;
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+
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+ /* Qword 2 */
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+ __le16 status_error1;
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+ u8 flex_flags2;
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+ u8 time_stamp_low;
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+ __le16 l2tag2_1st;
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+ __le16 l2tag2_2nd;
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+
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+ /* Qword 3 */
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+ __le16 flex_meta2;
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+ __le16 flex_meta3;
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+ union {
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+ struct {
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+ __le16 flex_meta4;
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+ __le16 flex_meta5;
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+ } flex;
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+ __le32 ts_high;
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+ } flex_ts;
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+ } wb; /* writeback */
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+};
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+
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+/* Rx Flex Descriptor for Comms Package Profile
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+ * RxDID Profile ID 16-21
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+ * Flex-field 0: RSS hash lower 16-bits
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+ * Flex-field 1: RSS hash upper 16-bits
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+ * Flex-field 2: Flow ID lower 16-bits
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+ * Flex-field 3: Flow ID upper 16-bits
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+ * Flex-field 4: AUX0
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+ * Flex-field 5: AUX1
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+ */
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+struct iavf_32b_rx_flex_desc_comms {
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+ /* Qword 0 */
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+ u8 rxdid;
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+ u8 mir_id_umb_cast;
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+ __le16 ptype_flexi_flags0;
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+ __le16 pkt_len;
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+ __le16 hdr_len_sph_flex_flags1;
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+
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+ /* Qword 1 */
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+ __le16 status_error0;
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+ __le16 l2tag1;
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+ __le32 rss_hash;
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+
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+ /* Qword 2 */
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+ __le16 status_error1;
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+ u8 flexi_flags2;
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+ u8 ts_low;
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+ __le16 l2tag2_1st;
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+ __le16 l2tag2_2nd;
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+
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+ /* Qword 3 */
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+ __le32 flow_id;
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+ union {
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+ struct {
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+ __le16 aux0;
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+ __le16 aux1;
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+ } flex;
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+ __le32 ts_high;
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+ } flex_ts;
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+};
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+
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+/* Rx Flex Descriptor for Comms Package Profile
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+ * RxDID Profile ID 22-23 (swap Hash and FlowID)
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+ * Flex-field 0: Flow ID lower 16-bits
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+ * Flex-field 1: Flow ID upper 16-bits
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+ * Flex-field 2: RSS hash lower 16-bits
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+ * Flex-field 3: RSS hash upper 16-bits
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+ * Flex-field 4: AUX0
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+ * Flex-field 5: AUX1
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+ */
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+struct iavf_32b_rx_flex_desc_comms_ovs {
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+ /* Qword 0 */
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+ u8 rxdid;
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+ u8 mir_id_umb_cast;
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+ __le16 ptype_flexi_flags0;
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+ __le16 pkt_len;
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+ __le16 hdr_len_sph_flex_flags1;
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+
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+ /* Qword 1 */
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+ __le16 status_error0;
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+ __le16 l2tag1;
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+ __le32 flow_id;
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+
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+ /* Qword 2 */
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+ __le16 status_error1;
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+ u8 flexi_flags2;
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+ u8 ts_low;
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+ __le16 l2tag2_1st;
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+ __le16 l2tag2_2nd;
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+
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+ /* Qword 3 */
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+ __le32 rss_hash;
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+ union {
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+ struct {
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+ __le16 aux0;
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+ __le16 aux1;
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+ } flex;
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+ __le32 ts_high;
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+ } flex_ts;
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+};
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+
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+/* Receive Flex Descriptor profile IDs: There are a total
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+ * of 64 profiles where profile IDs 0/1 are for legacy; and
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+ * profiles 2-63 are flex profiles that can be programmed
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+ * with a specific metadata (profile 7 reserved for HW)
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+ */
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+enum iavf_rxdid {
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+ IAVF_RXDID_LEGACY_0 = 0,
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+ IAVF_RXDID_LEGACY_1 = 1,
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+ IAVF_RXDID_FLEX_NIC = 2,
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+ IAVF_RXDID_FLEX_NIC_2 = 6,
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+ IAVF_RXDID_HW = 7,
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+ IAVF_RXDID_COMMS_GENERIC = 16,
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+ IAVF_RXDID_COMMS_AUX_VLAN = 17,
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+ IAVF_RXDID_COMMS_AUX_IPV4 = 18,
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+ IAVF_RXDID_COMMS_AUX_IPV6 = 19,
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+ IAVF_RXDID_COMMS_AUX_IPV6_FLOW = 20,
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+ IAVF_RXDID_COMMS_AUX_TCP = 21,
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+ IAVF_RXDID_COMMS_OVS_1 = 22,
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+ IAVF_RXDID_COMMS_OVS_2 = 23,
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+ IAVF_RXDID_LAST = 63,
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+};
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+
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+enum iavf_rx_flex_desc_status_error_0_bits {
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+ /* Note: These are predefined bit offsets */
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+ IAVF_RX_FLEX_DESC_STATUS0_DD_S = 0,
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+ IAVF_RX_FLEX_DESC_STATUS0_EOF_S,
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+ IAVF_RX_FLEX_DESC_STATUS0_HBO_S,
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+ IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S,
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+ IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
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+ IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
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+ IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
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+ IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
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+ IAVF_RX_FLEX_DESC_STATUS0_LPBK_S,
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+ IAVF_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
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+ IAVF_RX_FLEX_DESC_STATUS0_RXE_S,
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+ IAVF_RX_FLEX_DESC_STATUS0_CRCP_S,
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+ IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
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+ IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
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+ IAVF_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
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+ IAVF_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
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+ IAVF_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
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+};
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+
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+/* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
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+#define IAVF_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */
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+
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+/* for iavf_32b_rx_flex_desc.pkt_len member */
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+#define IAVF_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */
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+
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int iavf_dev_rx_queue_setup(struct rte_eth_dev *dev,
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uint16_t queue_idx,
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uint16_t nb_desc,
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--
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2.17.1
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