a4b10e5e86
Device speed capability should be specified based on different phy types instead of a fixed value, this patch fix the issue. Change-Id: Ia76231aefbcb0fe8370867b6e86a0d3bb9e169a0 Signed-off-by: Chenmin Sun <chenmin.sun@intel.com>
102 lines
4.1 KiB
Diff
102 lines
4.1 KiB
Diff
From 925981b21ca765b97540d273bd0362518eb2de48 Mon Sep 17 00:00:00 2001
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From: Chenmin Sun <chenmin.sun@intel.com>
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Date: Thu, 28 Mar 2019 04:51:19 +0800
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Subject: [PATCH] net/ice: fixed speed capability error issue
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Device speed capability should be specified based on different phy types
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instead of a fixed value, this patch fix the issue.
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Signed-off-by: Chenmin Sun <chenmin.sun@intel.com>
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---
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drivers/net/ice/ice_ethdev.c | 17 +++++++++++----
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drivers/net/ice/ice_ethdev.h | 40 ++++++++++++++++++++++++++++++++++++
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2 files changed, 53 insertions(+), 4 deletions(-)
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diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
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index 6ab66faeb..1073eb501 100644
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--- a/drivers/net/ice/ice_ethdev.c
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+++ b/drivers/net/ice/ice_ethdev.c
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@@ -1819,6 +1819,8 @@ ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
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struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct ice_vsi *vsi = pf->main_vsi;
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struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
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+ u64 phy_type_low;
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+ u64 phy_type_high;
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dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
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dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
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@@ -1898,10 +1900,17 @@ ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
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ETH_LINK_SPEED_5G |
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ETH_LINK_SPEED_10G |
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ETH_LINK_SPEED_20G |
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- ETH_LINK_SPEED_25G |
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- ETH_LINK_SPEED_40G |
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- ETH_LINK_SPEED_50G |
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- ETH_LINK_SPEED_100G;
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+ ETH_LINK_SPEED_25G;
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+
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+ phy_type_low = hw->port_info->phy.phy_type_low;
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+ phy_type_high = hw->port_info->phy.phy_type_high;
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+
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+ if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
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+ dev_info->speed_capa |= ETH_LINK_SPEED_50G;
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+
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+ if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
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+ ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
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+ dev_info->speed_capa |= ETH_LINK_SPEED_100G;
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dev_info->nb_rx_queues = dev->data->nb_rx_queues;
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dev_info->nb_tx_queues = dev->data->nb_tx_queues;
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diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h
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index 3cefa5b5b..249fbef20 100644
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--- a/drivers/net/ice/ice_ethdev.h
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+++ b/drivers/net/ice/ice_ethdev.h
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@@ -315,4 +315,44 @@ ice_align_floor(int n)
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return 0;
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return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
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}
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+
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+#define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \
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+ (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1))
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+
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+#define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \
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+ (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \
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+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR))
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+
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+#define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \
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+ (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \
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+ ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \
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+ ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \
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+ ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \
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+ ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2))
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+
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#endif /* _ICE_ETHDEV_H_ */
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--
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2.17.1
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