186798270a
CQE flags located in bits 16-31 at offset 0x1c should be defined as actual numbers instead of indexes. Besides, L3 header type for IPv4 is 10(2 in decimal) and for IPv6 is 01(1 in decimal) according to CQE entry fields description of page 120 in Mellanox Programmer Reference Manual. (https://network.nvidia.com/files/doc-2020/ethernet-adapters-programming-manual.pdf) Fixing this issue will lead to correct CQE flags printing for rdma-input node when buffer trace is enabled. Type: fix Signed-off-by: Jieqiang Wang <jieqiang.wang@arm.com> Change-Id: I9b578ca5cbd8cd93a577aa83131e31c79f60430e
173 lines
4.2 KiB
C
173 lines
4.2 KiB
C
/*
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*------------------------------------------------------------------
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* Copyright (c) 2020 Cisco and/or its affiliates.
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*------------------------------------------------------------------
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*/
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#ifndef _RDMA_MLX5DV_H_
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#define _RDMA_MLX5DV_H_
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#undef always_inline
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#include <infiniband/mlx5dv.h>
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#define always_inline static_always_inline
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#include <vppinfra/types.h>
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#include <vppinfra/error.h>
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/* CQE flags - bits 16-31 of qword at offset 0x1c */
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#define CQE_FLAG_L4_OK (1 << 10)
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#define CQE_FLAG_L3_OK (1 << 9)
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#define CQE_FLAG_L2_OK (1 << 8)
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#define CQE_FLAG_IP_FRAG (1 << 7)
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#define CQE_FLAG_L4_HDR_TYPE(f) (((f) >> 4) & 7)
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#define CQE_FLAG_L3_HDR_TYPE_SHIFT (2)
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#define CQE_FLAG_L3_HDR_TYPE_MASK (3 << CQE_FLAG_L3_HDR_TYPE_SHIFT)
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#define CQE_FLAG_L3_HDR_TYPE(f) (((f) & CQE_FLAG_L3_HDR_TYPE_MASK) >> CQE_FLAG_L3_HDR_TYPE_SHIFT)
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#define CQE_FLAG_L3_HDR_TYPE_IP4 2
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#define CQE_FLAG_L3_HDR_TYPE_IP6 1
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#define CQE_FLAG_IP_EXT_OPTS 1
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/* CQE byte count (Striding RQ) */
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#define CQE_BC_FILLER_MASK (1 << 31)
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#define CQE_BC_CONSUMED_STRIDES_SHIFT (16)
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#define CQE_BC_CONSUMED_STRIDES_MASK (0x3fff << CQE_BC_CONSUMED_STRIDES_SHIFT)
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#define CQE_BC_BYTE_COUNT_MASK (0xffff)
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typedef struct
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{
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struct
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{
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u8 pad1[28];
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u16 flags;
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u8 pad2[14];
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union
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{
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u32 byte_cnt;
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u32 mini_cqe_num;
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};
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u8 pad3[12];
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u16 wqe_counter;
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u8 signature;
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u8 opcode_cqefmt_se_owner;
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};
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} mlx5dv_cqe_t;
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STATIC_ASSERT_SIZEOF (mlx5dv_cqe_t, 64);
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typedef struct
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{
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union
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{
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u32 checksum;
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u32 rx_hash_result;
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};
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u32 byte_count;
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} mlx5dv_mini_cqe_t;
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typedef struct
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{
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u64 dsz_and_lkey;
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u64 addr;
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} mlx5dv_wqe_ds_t; /* a WQE data segment */
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typedef struct
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{
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u8 rsvd0[2];
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u16 next_wqe_index;
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u8 signature;
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u8 rsvd1[11];
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} mlx5dv_wqe_srq_next_t;
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#define foreach_cqe_rx_field \
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_(0x1c, 26, 26, l4_ok) \
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_(0x1c, 25, 25, l3_ok) \
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_(0x1c, 24, 24, l2_ok) \
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_(0x1c, 23, 23, ip_frag) \
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_(0x1c, 22, 20, l4_hdr_type) \
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_(0x1c, 19, 18, l3_hdr_type) \
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_(0x1c, 17, 17, ip_ext_opts) \
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_(0x1c, 16, 16, cv) \
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_(0x2c, 31, 0, byte_cnt) \
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_(0x30, 63, 0, timestamp) \
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_(0x38, 31, 24, rx_drop_counter) \
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_(0x38, 23, 0, flow_tag) \
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_(0x3c, 31, 16, wqe_counter) \
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_(0x3c, 15, 8, signature) \
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_(0x3c, 7, 4, opcode) \
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_(0x3c, 3, 2, cqe_format) \
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_(0x3c, 1, 1, sc) \
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_(0x3c, 0, 0, owner)
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/* inline functions */
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static inline u32
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mlx5_get_u32 (void *start, int offset)
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{
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return clib_net_to_host_u32 (*(u32 *) (((u8 *) start) + offset));
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}
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static inline u64
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mlx5_get_u64 (void *start, int offset)
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{
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return clib_net_to_host_u64 (*(u64 *) (((u8 *) start) + offset));
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}
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static inline void
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mlx5_set_u32 (void *start, int offset, u32 value)
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{
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(*(u32 *) (((u8 *) start) + offset)) = clib_host_to_net_u32 (value);
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}
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static inline void
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mlx5_set_u64 (void *start, int offset, u64 value)
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{
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(*(u64 *) (((u8 *) start) + offset)) = clib_host_to_net_u64 (value);
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}
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static inline void
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mlx5_set_bits (void *start, int offset, int first, int last, u32 value)
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{
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u32 mask = (1 << (first - last + 1)) - 1;
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u32 old = mlx5_get_u32 (start, offset);
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if ((last == 0) && (first == 31))
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{
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mlx5_set_u32 (start, offset, value);
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return;
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}
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ASSERT (value == (value & mask));
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value &= mask;
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old &= ~(mask << last);
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mlx5_set_u32 (start, offset, old | value << last);
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}
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static inline u32
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mlx5_get_bits (void *start, int offset, int first, int last)
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{
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u32 value = mlx5_get_u32 (start, offset);
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if ((last == 0) && (first == 31))
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return value;
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value >>= last;
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value &= (1 << (first - last + 1)) - 1;
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return value;
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}
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#endif /* RDMA_MLX5DV_H */
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/*
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* fd.io coding-style-patch-verification: ON
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*
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* Local Variables:
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* eval: (c-set-style "gnu")
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* End:
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*/
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