2023-07-21 09:17:39 +10:00
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/* Copyright 2018 ishtob
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* Driver for DRV2605L written for QMK
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <stdint.h>
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/* Initialization settings
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* Feedback Control Settings */
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_FB_ERM_LRA
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# define DRV2605L_FB_ERM_LRA 1 /* For ERM:0 or LRA:1*/
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2023-07-21 09:17:39 +10:00
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_FB_BRAKEFACTOR
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# define DRV2605L_FB_BRAKEFACTOR 3 /* For 1x:0, 2x:1, 3x:2, 4x:3, 6x:4, 8x:5, 16x:6, Disable Braking:7 */
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2023-07-21 09:17:39 +10:00
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_FB_LOOPGAIN
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# define DRV2605L_FB_LOOPGAIN 1 /* For Low:0, Medium:1, High:2, Very High:3 */
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2023-07-21 09:17:39 +10:00
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#endif
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/* LRA specific settings */
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2023-08-04 10:16:16 +10:00
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#if DRV2605L_FB_ERM_LRA == 1
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# ifndef DRV2605L_V_RMS
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# define DRV2605L_V_RMS 2.0
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2023-07-21 09:17:39 +10:00
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# endif
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2023-08-04 10:16:16 +10:00
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# ifndef DRV2605L_V_PEAK
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# define DRV2605L_V_PEAK 2.1
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2023-07-21 09:17:39 +10:00
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# endif
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2023-08-04 10:16:16 +10:00
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# ifndef DRV2605L_F_LRA
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# define DRV2605L_F_LRA 205
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2023-07-21 09:17:39 +10:00
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# endif
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2023-08-04 10:16:16 +10:00
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# ifndef DRV2605L_RATED_VOLTAGE
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# define DRV2605L_RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */
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2023-07-21 09:17:39 +10:00
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# endif
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_RATED_VOLTAGE
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# define DRV2605L_RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */
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2023-07-21 09:17:39 +10:00
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_V_PEAK
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# define DRV2605L_V_PEAK 2.8
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2023-07-21 09:17:39 +10:00
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#endif
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/* Library Selection */
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#ifndef DRV2605L_LIBRARY
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2023-08-04 10:16:16 +10:00
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# if DRV2605L_FB_ERM_LRA == 1
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2023-07-21 09:17:39 +10:00
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# define DRV2605L_LIBRARY 6 /* For Empty:0' TS2200 library A to D:1-5, LRA Library: 6 */
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# else
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# define DRV2605L_LIBRARY 1
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# endif
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#endif
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#ifndef DRV2605L_GREETING
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# define DRV2605L_GREETING DRV2605L_EFFECT_750_MS_ALERT_100
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#endif
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#ifndef DRV2605L_DEFAULT_MODE
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# define DRV2605L_DEFAULT_MODE DRV2605L_EFFECT_STRONG_CLICK_1_100
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#endif
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/* Control 1 register settings */
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_DRIVE_TIME
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# define DRV2605L_DRIVE_TIME 25
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_AC_COUPLE
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# define DRV2605L_AC_COUPLE 0
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2023-07-21 09:17:39 +10:00
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_STARTUP_BOOST
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# define DRV2605L_STARTUP_BOOST 1
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2023-07-21 09:17:39 +10:00
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#endif
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/* Control 2 Settings */
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_BIDIR_INPUT
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# define DRV2605L_BIDIR_INPUT 1
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2023-07-21 09:17:39 +10:00
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_BRAKE_STAB
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# define DRV2605L_BRAKE_STAB 1 /* Loopgain is reduced when braking is almost complete to improve stability */
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2023-07-21 09:17:39 +10:00
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_SAMPLE_TIME
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# define DRV2605L_SAMPLE_TIME 3
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2023-07-21 09:17:39 +10:00
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_BLANKING_TIME
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# define DRV2605L_BLANKING_TIME 1
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2023-07-21 09:17:39 +10:00
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_IDISS_TIME
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# define DRV2605L_IDISS_TIME 1
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2023-07-21 09:17:39 +10:00
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#endif
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/* Control 3 settings */
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_NG_THRESH
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# define DRV2605L_NG_THRESH 2
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_ERM_OPEN_LOOP
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# define DRV2605L_ERM_OPEN_LOOP 1
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_SUPPLY_COMP_DIS
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# define DRV2605L_SUPPLY_COMP_DIS 0
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_DATA_FORMAT_RTO
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# define DRV2605L_DATA_FORMAT_RTO 0
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2023-07-21 09:17:39 +10:00
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_LRA_DRIVE_MODE
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# define DRV2605L_LRA_DRIVE_MODE 0
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_N_PWM_ANALOG
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# define DRV2605L_N_PWM_ANALOG 0
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#endif
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_LRA_OPEN_LOOP
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# define DRV2605L_LRA_OPEN_LOOP 0
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#endif
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/* Control 4 settings */
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2023-08-04 10:16:16 +10:00
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#ifndef DRV2605L_ZC_DET_TIME
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# define DRV2605L_ZC_DET_TIME 0
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#endif
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#ifndef DRV2605L_AUTO_CAL_TIME
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# define DRV2605L_AUTO_CAL_TIME 3
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#endif
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#define DRV2605L_I2C_ADDRESS 0x5A
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#define DRV2605L_REG_STATUS 0x00
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#define DRV2605L_REG_MODE 0x01
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#define DRV2605L_REG_RTP_INPUT 0x02
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#define DRV2605L_REG_LIBRARY_SELECTION 0x03
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_1 0x04
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_2 0x05
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_3 0x06
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_4 0x07
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_5 0x08
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_6 0x09
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_7 0x0A
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_8 0x0B
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#define DRV2605L_REG_GO 0x0C
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#define DRV2605L_REG_OVERDRIVE_TIME_OFFSET 0x0D
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#define DRV2605L_REG_SUSTAIN_TIME_OFFSET_P 0x0E
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#define DRV2605L_REG_SUSTAIN_TIME_OFFSET_N 0x0F
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#define DRV2605L_REG_BRAKE_TIME_OFFSET 0x10
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#define DRV2605L_REG_AUDIO_TO_VIBE_CTRL 0x11
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#define DRV2605L_REG_AUDIO_TO_VIBE_MIN_INPUT 0x12
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#define DRV2605L_REG_AUDIO_TO_VIBE_MAX_INPUT 0x13
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#define DRV2605L_REG_AUDIO_TO_VIBE_MIN_OUTPUT_DRIVE 0x14
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#define DRV2605L_REG_AUDIO_TO_VIBE_MAX_OUTPUT_DRIVE 0x15
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#define DRV2605L_REG_RATED_VOLTAGE 0x16
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#define DRV2605L_REG_OVERDRIVE_CLAMP_VOLTAGE 0x17
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#define DRV2605L_REG_AUTO_CALIBRATION_COMPENSATION_RESULT 0x18
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#define DRV2605L_REG_AUTO_CALIBRATION_BACK_EMF_RESULT 0x19
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#define DRV2605L_REG_FEEDBACK_CTRL 0x1A
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#define DRV2605L_REG_CTRL1 0x1B
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#define DRV2605L_REG_CTRL2 0x1C
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#define DRV2605L_REG_CTRL3 0x1D
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#define DRV2605L_REG_CTRL4 0x1E
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#define DRV2605L_REG_CTRL5 0x1F
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#define DRV2605L_REG_LRA_OPEN_LOOP_PERIOD 0x20
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#define DRV2605L_REG_VBAT_VOLTAGE_MONITOR 0x21
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#define DRV2605L_REG_LRA_RESONANCE_PERIOD 0x22
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void drv2605l_init(void);
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void drv2605l_write(const uint8_t reg_addr, const uint8_t data);
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uint8_t drv2605l_read(const uint8_t reg_addr);
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void drv2605l_rtp_init(void);
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void drv2605l_amplitude(const uint8_t amplitude);
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void drv2605l_pulse(const uint8_t sequence);
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2023-08-04 10:16:16 +10:00
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typedef enum drv2605l_effect_t {
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DRV2605L_EFFECT_CLEAR_SEQUENCE,
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DRV2605L_EFFECT_STRONG_CLICK_100,
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DRV2605L_EFFECT_STRONG_CLICK_60,
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DRV2605L_EFFECT_STRONG_CLICK_30,
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DRV2605L_EFFECT_SHARP_CLICK_100,
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DRV2605L_EFFECT_SHARP_CLICK_60,
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DRV2605L_EFFECT_SHARP_CLICK_30,
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DRV2605L_EFFECT_SOFT_BUMP_100,
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DRV2605L_EFFECT_SOFT_BUMP_60,
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DRV2605L_EFFECT_SOFT_BUMP_30,
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DRV2605L_EFFECT_DOUBLE_CLICK_100,
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DRV2605L_EFFECT_DOUBLE_CLICK_60,
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DRV2605L_EFFECT_TRIPLE_CLICK_100,
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DRV2605L_EFFECT_SOFT_FUZZ_60,
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DRV2605L_EFFECT_STRONG_BUZZ_100,
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DRV2605L_EFFECT_750_MS_ALERT_100,
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DRV2605L_EFFECT_1000_MS_ALERT_100,
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DRV2605L_EFFECT_STRONG_CLICK_1_100,
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DRV2605L_EFFECT_STRONG_CLICK_2_80,
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DRV2605L_EFFECT_STRONG_CLICK_3_60,
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DRV2605L_EFFECT_STRONG_CLICK_4_30,
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DRV2605L_EFFECT_MEDIUM_CLICK_1_100,
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DRV2605L_EFFECT_MEDIUM_CLICK_2_80,
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DRV2605L_EFFECT_MEDIUM_CLICK_3_60,
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DRV2605L_EFFECT_SHARP_TICK_1_100,
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DRV2605L_EFFECT_SHARP_TICK_2_80,
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DRV2605L_EFFECT_SHARP_TICK_3_60,
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DRV2605L_EFFECT_SHORT_DOUBLE_CLICK_STRONG_1_100,
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DRV2605L_EFFECT_SHORT_DOUBLE_CLICK_STRONG_2_80,
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DRV2605L_EFFECT_SHORT_DOUBLE_CLICK_STRONG_3_60,
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DRV2605L_EFFECT_SHORT_DOUBLE_CLICK_STRONG_4_30,
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DRV2605L_EFFECT_SHORT_DOUBLE_CLICK_MEDIUM_1_100,
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DRV2605L_EFFECT_SHORT_DOUBLE_CLICK_MEDIUM_2_80,
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DRV2605L_EFFECT_SHORT_DOUBLE_CLICK_MEDIUM_3_60,
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DRV2605L_EFFECT_SHORT_DOUBLE_SHARP_TICK_1_100,
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DRV2605L_EFFECT_SHORT_DOUBLE_SHARP_TICK_2_80,
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DRV2605L_EFFECT_SHORT_DOUBLE_SHARP_TICK_3_60,
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DRV2605L_EFFECT_LONG_DOUBLE_SHARP_CLICK_STRONG_1_100,
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DRV2605L_EFFECT_LONG_DOUBLE_SHARP_CLICK_STRONG_2_80,
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DRV2605L_EFFECT_LONG_DOUBLE_SHARP_CLICK_STRONG_3_60,
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DRV2605L_EFFECT_LONG_DOUBLE_SHARP_CLICK_STRONG_4_30,
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DRV2605L_EFFECT_LONG_DOUBLE_SHARP_CLICK_MEDIUM_1_100,
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DRV2605L_EFFECT_LONG_DOUBLE_SHARP_CLICK_MEDIUM_2_80,
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DRV2605L_EFFECT_LONG_DOUBLE_SHARP_CLICK_MEDIUM_3_60,
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DRV2605L_EFFECT_LONG_DOUBLE_SHARP_TICK_1_100,
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DRV2605L_EFFECT_LONG_DOUBLE_SHARP_TICK_2_80,
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DRV2605L_EFFECT_LONG_DOUBLE_SHARP_TICK_3_60,
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DRV2605L_EFFECT_BUZZ_1_100,
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DRV2605L_EFFECT_BUZZ_2_80,
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DRV2605L_EFFECT_BUZZ_3_60,
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DRV2605L_EFFECT_BUZZ_4_40,
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DRV2605L_EFFECT_BUZZ_5_20,
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DRV2605L_EFFECT_PULSING_STRONG_1_100,
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DRV2605L_EFFECT_PULSING_STRONG_2_60,
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DRV2605L_EFFECT_PULSING_MEDIUM_1_100,
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DRV2605L_EFFECT_PULSING_MEDIUM_2_60,
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DRV2605L_EFFECT_PULSING_SHARP_1_100,
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DRV2605L_EFFECT_PULSING_SHARP_2_60,
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DRV2605L_EFFECT_TRANSITION_CLICK_1_100,
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DRV2605L_EFFECT_TRANSITION_CLICK_2_80,
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DRV2605L_EFFECT_TRANSITION_CLICK_3_60,
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DRV2605L_EFFECT_TRANSITION_CLICK_4_40,
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DRV2605L_EFFECT_TRANSITION_CLICK_5_20,
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DRV2605L_EFFECT_TRANSITION_CLICK_6_10,
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DRV2605L_EFFECT_TRANSITION_HUM_1_100,
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DRV2605L_EFFECT_TRANSITION_HUM_2_80,
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DRV2605L_EFFECT_TRANSITION_HUM_3_60,
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DRV2605L_EFFECT_TRANSITION_HUM_4_40,
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DRV2605L_EFFECT_TRANSITION_HUM_5_20,
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DRV2605L_EFFECT_TRANSITION_HUM_6_10,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SMOOTH_1_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SMOOTH_2_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SMOOTH_1_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SMOOTH_2_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SMOOTH_1_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SMOOTH_2_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SHARP_1_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SHARP_2_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SHARP_1_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SHARP_2_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SHARP_1_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SHARP_2_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SMOOTH_1_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SMOOTH_2_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SMOOTH_1_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SMOOTH_2_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SMOOTH_1_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SMOOTH_2_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SHARP_1_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SHARP_2_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SHARP_1_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SHARP_2_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SHARP_1_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SHARP_2_100,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SMOOTH_1_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SMOOTH_2_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SMOOTH_1_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SMOOTH_2_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SMOOTH_1_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SMOOTH_2_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SHARP_1_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SHARP_2_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SHARP_1_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SHARP_2_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SHARP_1_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SHARP_2_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SMOOTH_1_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SMOOTH_2_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SMOOTH_1_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SMOOTH_2_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SMOOTH_1_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SMOOTH_2_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SHARP_1_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SHARP_2_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SHARP_1_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SHARP_2_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SHARP_1_50,
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DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SHARP_2_50,
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DRV2605L_EFFECT_LONG_BUZZ_FOR_PROGRAMMATIC_STOPPING,
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DRV2605L_EFFECT_SMOOTH_HUM_1_50,
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DRV2605L_EFFECT_SMOOTH_HUM_2_40,
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DRV2605L_EFFECT_SMOOTH_HUM_3_30,
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DRV2605L_EFFECT_SMOOTH_HUM_4_20,
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DRV2605L_EFFECT_SMOOTH_HUM_5_10,
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DRV2605L_EFFECT_COUNT
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} drv2605l_effect_t;
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2023-07-21 09:17:39 +10:00
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/* Register bit array unions */
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2023-08-04 10:16:16 +10:00
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typedef union { /* register 0x1A */
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uint8_t raw;
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2023-07-21 09:17:39 +10:00
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struct {
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uint8_t BEMF_GAIN : 2;
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uint8_t LOOP_GAIN : 2;
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uint8_t BRAKE_FACTOR : 3;
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uint8_t ERM_LRA : 1;
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2023-08-04 10:16:16 +10:00
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} bits;
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} drv2605l_reg_feedback_ctrl_t;
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2023-07-21 09:17:39 +10:00
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2023-08-04 10:16:16 +10:00
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typedef union { /* register 0x1B */
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uint8_t raw;
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2023-07-21 09:17:39 +10:00
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struct {
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uint8_t C1_DRIVE_TIME : 5;
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uint8_t C1_AC_COUPLE : 1;
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uint8_t : 1;
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uint8_t C1_STARTUP_BOOST : 1;
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2023-08-04 10:16:16 +10:00
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} bits;
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} drv2605l_reg_ctrl1_t;
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2023-07-21 09:17:39 +10:00
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2023-08-04 10:16:16 +10:00
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typedef union { /* register 0x1C */
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uint8_t raw;
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2023-07-21 09:17:39 +10:00
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struct {
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uint8_t C2_IDISS_TIME : 2;
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uint8_t C2_BLANKING_TIME : 2;
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uint8_t C2_SAMPLE_TIME : 2;
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uint8_t C2_BRAKE_STAB : 1;
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uint8_t C2_BIDIR_INPUT : 1;
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2023-08-04 10:16:16 +10:00
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} bits;
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} drv2605l_reg_ctrl2_t;
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2023-07-21 09:17:39 +10:00
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2023-08-04 10:16:16 +10:00
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typedef union { /* register 0x1D */
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uint8_t raw;
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2023-07-21 09:17:39 +10:00
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struct {
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uint8_t C3_LRA_OPEN_LOOP : 1;
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uint8_t C3_N_PWM_ANALOG : 1;
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uint8_t C3_LRA_DRIVE_MODE : 1;
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uint8_t C3_DATA_FORMAT_RTO : 1;
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uint8_t C3_SUPPLY_COMP_DIS : 1;
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uint8_t C3_ERM_OPEN_LOOP : 1;
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uint8_t C3_NG_THRESH : 2;
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2023-08-04 10:16:16 +10:00
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} bits;
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} drv2605l_reg_ctrl3_t;
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2023-07-21 09:17:39 +10:00
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2023-08-04 10:16:16 +10:00
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typedef union { /* register 0x1E */
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uint8_t raw;
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2023-07-21 09:17:39 +10:00
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struct {
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uint8_t C4_OTP_PROGRAM : 1;
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uint8_t : 1;
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uint8_t C4_OTP_STATUS : 1;
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uint8_t : 1;
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uint8_t C4_AUTO_CAL_TIME : 2;
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uint8_t C4_ZC_DET_TIME : 2;
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2023-08-04 10:16:16 +10:00
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} bits;
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} drv2605l_reg_ctrl4_t;
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