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Add LM3S811 Keil/RVDS demo files.

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This commit is contained in:
Richard Barry
2006-09-24 10:06:47 +00:00
parent 7508aa6219
commit 51204ddced
41 changed files with 7149 additions and 0 deletions
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76
Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h Normal file
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/*
FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7000 ) )
#define configMAX_TASK_NAME_LEN ( 3 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_CO_ROUTINES 0
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 0
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

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Demo/CORTEX_LM3S811_KEIL/LuminaryCode/DriverLib.h Normal file
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#ifndef DRIVER_LIB_H
#define DRIVER_LIB_H
#include "DriverLib.h"
#include "hw_adc.h"
#include "hw_comp.h"
#include "hw_flash.h"
#include "hw_gpio.h"
#include "hw_i2c.h"
#include "hw_ints.h"
#include "hw_memmap.h"
#include "hw_nvic.h"
#include "hw_pwm.h"
#include "hw_qei.h"
#include "hw_ssi.h"
#include "hw_sysctl.h"
#include "hw_timer.h"
#include "hw_types.h"
#include "hw_uart.h"
#include "hw_watchdog.h"
#include "osram96x16.h"
#include "src\adc.h"
#include "src\comp.h"
#include "src\cpu.h"
#include "src\debug.h"
#include "src\flash.h"
#include "src\gpio.h"
#include "src\i2c.h"
#include "src\interrupt.h"
#include "src\pwm.h"
#include "src\qei.h"
#include "src\ssi.h"
#include "src\sysctl.h"
#include "src\systick.h"
#include "src\timer.h"
#include "src\uart.h"
#include "src\watchdog.h"
#endif

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Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_adc.h Normal file
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Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_comp.h Normal file
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//*****************************************************************************
//
// hw_comp.h - Macros used when accessing the comparator hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_COMP_H__
#define __HW_COMP_H__
//*****************************************************************************
//
// The following define the offsets of the comparator registers.
//
//*****************************************************************************
#define COMP_O_MIS 0x00000000 // Interrupt status register
#define COMP_O_RIS 0x00000004 // Raw interrupt status register
#define COMP_O_INTEN 0x00000008 // Interrupt enable register
#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.
#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register
#define COMP_O_ACCTL0 0x00000024 // Comp0 control register
#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register
#define COMP_O_ACCTL1 0x00000044 // Comp1 control register
#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register
#define COMP_O_ACCTL2 0x00000064 // Comp2 control register
//*****************************************************************************
//
// The following define the bit fields in the COMP_MIS, COMP_RIS, and
// COMP_INTEN registers.
//
//*****************************************************************************
#define COMP_INT_2 0x00000004 // Comp2 interrupt
#define COMP_INT_1 0x00000002 // Comp1 interrupt
#define COMP_INT_0 0x00000001 // Comp0 interrupt
//*****************************************************************************
//
// The following define the bit fields in the COMP_REFCTL register.
//
//*****************************************************************************
#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable
#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range
#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask
#define COMP_REFCTL_VREF_SHIFT 0
//*****************************************************************************
//
// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and
// COMP_ACSTAT2 registers.
//
//*****************************************************************************
#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value
//*****************************************************************************
//
// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and
// COMP_ACCTL2 registers.
//
//*****************************************************************************
#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable
#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask
#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved
#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable
#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select
#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask
#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense
#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge
#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge
#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges
#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select
#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask
#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense
#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge
#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge
#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges
#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert
//*****************************************************************************
//
// The following define the reset values for the comparator registers.
//
//*****************************************************************************
#define COMP_RV_MIS 0x00000000 // Interrupt status register
#define COMP_RV_RIS 0x00000000 // Raw interrupt status register
#define COMP_RV_INTEN 0x00000000 // Interrupt enable register
#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.
#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register
#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register
#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register
#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register
#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register
#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register
#endif // __HW_COMP_H__

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//*****************************************************************************
//
// hw_flash.h - Macros used when accessing the flash controller.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_FLASH_H__
#define __HW_FLASH_H__
//*****************************************************************************
//
// The following define the offsets of the FLASH registers.
//
//*****************************************************************************
#define FLASH_FMA 0x400FD000 // Memory address register
#define FLASH_FMD 0x400FD004 // Memory data register
#define FLASH_FMC 0x400FD008 // Memory control register
#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register
#define FLASH_FCIM 0x400FD010 // Interrupt mask register
#define FLASH_FCMISC 0x400FD014 // Interrupt status register
#define FLASH_FMPRE 0x400FE130 // FLASH read protect register
#define FLASH_FMPPE 0x400FE134 // FLASH program protect register
#define FLASH_USECRL 0x400FE140 // uSec reload register
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FMC register.
//
//*****************************************************************************
#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask
#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
#define FLASH_FMC_COMT 0x00000008 // Commit user register
#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH
#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page
#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FCRIS register.
//
//*****************************************************************************
#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status
#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FCIM register.
//
//*****************************************************************************
#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask
#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FMIS register.
//
//*****************************************************************************
#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status
#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE
// registers.
//
//*****************************************************************************
#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31
#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30
#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29
#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28
#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27
#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26
#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25
#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24
#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23
#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22
#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21
#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20
#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19
#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18
#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17
#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16
#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15
#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14
#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13
#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12
#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11
#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10
#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9
#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8
#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7
#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6
#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5
#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4
#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3
#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2
#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1
#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0
//*****************************************************************************
//
// The following define the bit fields in the FLASH_USECRL register.
//
//*****************************************************************************
#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec
#define FLASH_USECRL_SHIFT 0
//*****************************************************************************
//
// The erase size is the size of the FLASH block that is erased by an erase
// operation, and the protect size is the size of the FLASH block that is
// protected by each protection register.
//
//*****************************************************************************
#define FLASH_ERASE_SIZE 0x00000400
#define FLASH_PROTECT_SIZE 0x00000800
#endif // __HW_FLASH_H__

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//*****************************************************************************
//
// hw_gpio.h - Defines and Macros for GPIO hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_GPIO_H__
#define __HW_GPIO_H__
//*****************************************************************************
//
// GPIO Register Offsets.
//
//*****************************************************************************
#define GPIO_O_DATA 0x00000000 // Data register.
#define GPIO_O_DIR 0x00000400 // Data direction register.
#define GPIO_O_IS 0x00000404 // Interrupt sense register.
#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.
#define GPIO_O_IEV 0x0000040C // Intterupt event register.
#define GPIO_O_IM 0x00000410 // Interrupt mask register.
#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.
#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.
#define GPIO_O_ICR 0x0000041C // Interrupt clear register.
#define GPIO_O_AFSEL 0x00000420 // Mode control select register.
#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.
#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.
#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.
#define GPIO_O_ODR 0x0000050C // Open drain select register.
#define GPIO_O_PUR 0x00000510 // Pull up select register.
#define GPIO_O_PDR 0x00000514 // Pull down select register.
#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.
#define GPIO_O_DEN 0x0000051C // Digital input enable register.
#define GPIO_O_PeriphID4 0x00000FD0 //
#define GPIO_O_PeriphID5 0x00000FD4 //
#define GPIO_O_PeriphID6 0x00000FD8 //
#define GPIO_O_PeriphID7 0x00000FDC //
#define GPIO_O_PeriphID0 0x00000FE0 //
#define GPIO_O_PeriphID1 0x00000FE4 //
#define GPIO_O_PeriphID2 0x00000FE8 //
#define GPIO_O_PeriphID3 0x00000FEC //
#define GPIO_O_PCellID0 0x00000FF0 //
#define GPIO_O_PCellID1 0x00000FF4 //
#define GPIO_O_PCellID2 0x00000FF8 //
#define GPIO_O_PCellID3 0x00000FFC //
//*****************************************************************************
//
// GPIO Register reset values.
//
//*****************************************************************************
#define GPIO_RV_DATA 0x00000000 // Data register reset value.
#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.
#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.
#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.
#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.
#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.
#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.
#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.
#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.
#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.
#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.
#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.
#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.
#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.
#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.
#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.
#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.
#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.
#define GPIO_RV_PeriphID4 0x00000000 //
#define GPIO_RV_PeriphID5 0x00000000 //
#define GPIO_RV_PeriphID6 0x00000000 //
#define GPIO_RV_PeriphID7 0x00000000 //
#define GPIO_RV_PeriphID0 0x00000061 //
#define GPIO_RV_PeriphID1 0x00000010 //
#define GPIO_RV_PeriphID2 0x00000004 //
#define GPIO_RV_PeriphID3 0x00000000 //
#define GPIO_RV_PCellID0 0x0000000D //
#define GPIO_RV_PCellID1 0x000000F0 //
#define GPIO_RV_PCellID2 0x00000005 //
#define GPIO_RV_PCellID3 0x000000B1 //
#endif // __HW_GPIO_H__

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//*****************************************************************************
//
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_I2C_H__
#define __HW_I2C_H__
//*****************************************************************************
//
// The following defines the offset between the I2C master and slave registers.
//
//*****************************************************************************
#define I2C_O_SLAVE 0x00000800 // Offset from master to slave
//*****************************************************************************
//
// The following define the offsets of the I2C master registers.
//
//*****************************************************************************
#define I2C_MASTER_O_SA 0x00000000 // Slave address register
#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
#define I2C_MASTER_O_DR 0x00000008 // Data register
#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register
#define I2C_MASTER_O_CR 0x00000020 // Configuration register
//*****************************************************************************
//
// The following define the offsets of the I2C slave registers.
//
//*****************************************************************************
#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
#define I2C_SLAVE_O_DR 0x00000008 // Data register
#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
//*****************************************************************************
//
// The followng define the bit fields in the I2C master slave address register.
//
//*****************************************************************************
#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
#define I2C_MASTER_SA_RS 0x00000001 // Receive/send
#define I2C_MASTER_SA_SA_SHIFT 1
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Control and Status
// register.
//
//*****************************************************************************
#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
#define I2C_MASTER_CS_STOP 0x00000004 // Stop
#define I2C_MASTER_CS_START 0x00000002 // Start
#define I2C_MASTER_CS_RUN 0x00000001 // Run
#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
#define I2C_MASTER_CS_ERR_MASK 0x0000001C
//*****************************************************************************
//
// The following define values used in determining the contents of the I2C
// Master Timer Period register.
//
//*****************************************************************************
#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
#define I2C_SCL_STANDARD 100000 // SCL standard frequency
#define I2C_SCL_FAST 400000 // SCL fast frequency
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Interrupt Mask
// register.
//
//*****************************************************************************
#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Raw Interrupt Status
// register.
//
//*****************************************************************************
#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Masked Interrupt
// Status register.
//
//*****************************************************************************
#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Interrupt Clear
// register.
//
//*****************************************************************************
#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Configuration
// register.
//
//*****************************************************************************
#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Own Address register.
//
//*****************************************************************************
#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Control/Status
// register.
//
//*****************************************************************************
#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Interrupt Mask
// register.
//
//*****************************************************************************
#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Raw Interrupt Status
// register.
//
//*****************************************************************************
#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Masked Interrupt
// Status register.
//
//*****************************************************************************
#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Interrupt Clear
// register.
//
//*****************************************************************************
#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
#endif // __HW_I2C_H__

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//*****************************************************************************
//
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_INTS_H__
#define __HW_INTS_H__
//*****************************************************************************
//
// The following define the fault assignments.
//
//*****************************************************************************
#define FAULT_NMI 2 // NMI fault
#define FAULT_HARD 3 // Hard fault
#define FAULT_MPU 4 // MPU fault
#define FAULT_BUS 5 // Bus fault
#define FAULT_USAGE 6 // Usage fault
#define FAULT_SVCALL 11 // SVCall
#define FAULT_DEBUG 12 // Debug monitor
#define FAULT_PENDSV 14 // PendSV
#define FAULT_SYSTICK 15 // System Tick
//*****************************************************************************
//
// The following define the interrupt assignments.
//
//*****************************************************************************
#define INT_GPIOA 16 // GPIO Port A
#define INT_GPIOB 17 // GPIO Port B
#define INT_GPIOC 18 // GPIO Port C
#define INT_GPIOD 19 // GPIO Port D
#define INT_GPIOE 20 // GPIO Port E
#define INT_UART0 21 // UART0 Rx and Tx
#define INT_UART1 22 // UART1 Rx and Tx
#define INT_SSI 23 // SSI Rx and Tx
#define INT_I2C 24 // I2C Master and Slave
#define INT_PWM_FAULT 25 // PWM Fault
#define INT_PWM0 26 // PWM Generator 0
#define INT_PWM1 27 // PWM Generator 1
#define INT_PWM2 28 // PWM Generator 2
#define INT_QEI 29 // Quadrature Encoder
#define INT_ADC0 30 // ADC Sequence 0
#define INT_ADC1 31 // ADC Sequence 1
#define INT_ADC2 32 // ADC Sequence 2
#define INT_ADC3 33 // ADC Sequence 3
#define INT_WATCHDOG 34 // Watchdog timer
#define INT_TIMER0A 35 // Timer 0 subtimer A
#define INT_TIMER0B 36 // Timer 0 subtimer B
#define INT_TIMER1A 37 // Timer 1 subtimer A
#define INT_TIMER1B 38 // Timer 1 subtimer B
#define INT_TIMER2A 39 // Timer 2 subtimer A
#define INT_TIMER2B 40 // Timer 2 subtimer B
#define INT_COMP0 41 // Analog Comparator 0
#define INT_COMP1 42 // Analog Comparator 1
#define INT_COMP2 43 // Analog Comparator 2
#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
#define INT_FLASH 45 // FLASH Control
//*****************************************************************************
//
// The total number of interrupts.
//
//*****************************************************************************
#define NUM_INTERRUPTS 46
//*****************************************************************************
//
// The total number of priority levels.
//
//*****************************************************************************
#define NUM_PRIORITY 8
#define NUM_PRIORITY_BITS 3
#endif // __HW_INTS_H__

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//*****************************************************************************
//
// hw_memmap.h - Macros defining the memory map of Stellaris.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_MEMMAP_H__
#define __HW_MEMMAP_H__
//*****************************************************************************
//
// The following define the base address of the memories and peripherals.
//
//*****************************************************************************
#define FLASH_BASE 0x00000000 // FLASH memory
#define SRAM_BASE 0x20000000 // SRAM memory
#define WATCHDOG_BASE 0x40000000 // Watchdog
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
#define SSI_BASE 0x40008000 // SSI
#define UART0_BASE 0x4000C000 // UART0
#define UART1_BASE 0x4000D000 // UART1
#define I2C_MASTER_BASE 0x40020000 // I2C Master
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
#define PWM_BASE 0x40028000 // PWM
#define QEI_BASE 0x4002C000 // QEI
#define TIMER0_BASE 0x40030000 // Timer0
#define TIMER1_BASE 0x40031000 // Timer1
#define TIMER2_BASE 0x40032000 // Timer2
#define ADC_BASE 0x40038000 // ADC
#define COMP_BASE 0x4003C000 // Analog comparators
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
#define SYSCTL_BASE 0x400FE000 // System Control
#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
#endif // __HW_MEMMAP_H__

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//*****************************************************************************
//
// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_PWM_H__
#define __HW_PWM_H__
//*****************************************************************************
//
// PWM Module Register Offsets.
//
//*****************************************************************************
#define PWM_O_CTL 0x00000000 // PWM Master Control register
#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register
#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register
#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register
#define PWM_O_FAULT 0x00000010 // PWM Output Fault register
#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register
#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.
#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register
#define PWM_O_STATUS 0x00000020 // PWM Status register
//*****************************************************************************
//
// The following define the bit fields in the PWM Master Control register.
//
//*****************************************************************************
#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2
#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1
#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0
//*****************************************************************************
//
// The following define the bit fields in the PWM Time Base Sync register.
//
//*****************************************************************************
#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter
#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter
#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter
//*****************************************************************************
//
// The following define the bit fields in the PWM Output Enable register.
//
//*****************************************************************************
#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable
#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable
#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable
#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable
#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable
#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable
//*****************************************************************************
//
// The following define the bit fields in the PWM Inversion register.
//
//*****************************************************************************
#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert
#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert
#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert
#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert
#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert
#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert
//*****************************************************************************
//
// The following define the bit fields in the PWM Fault register.
//
//*****************************************************************************
#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault
#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault
#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault
#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault
#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault
#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault
//*****************************************************************************
//
// PWM Interrupt Register bit definitions.
//
//*****************************************************************************
#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending
//*****************************************************************************
//
// The following define the bit fields in the PWM Status register.
//
//*****************************************************************************
#define PWM_STATUS_FAULT 0x00000001 // Fault status
//*****************************************************************************
//
// PWM Generator standard offsets.
//
//*****************************************************************************
#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
#define PWM_O_X_CTL 0x00000000 // Gen Control Reg
#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
//*****************************************************************************
//
// PWM_X Control Register bit definitions.
//
//*****************************************************************************
#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block
#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down
#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode
#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg
#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg
#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg
//*****************************************************************************
//
// PWM_X Interrupt/Trigger Enable Register bit definitions.
//
//*****************************************************************************
#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0
#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD
#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U
#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D
#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U
#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D
#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0
#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD
#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U
#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D
#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U
#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D
//*****************************************************************************
//
// PWM_X Raw Interrupt Status Register bit definitions.
//
//*****************************************************************************
#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int
#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int
#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int
#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int
#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int
#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int
//*****************************************************************************
//
// PWM_X Interrupt Status Register bit definitions.
//
//*****************************************************************************
#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received
#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd
#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd
#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd
#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd
#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd
//*****************************************************************************
//
// PWM_X Generator A/B Control Register bit definitions.
//
//*****************************************************************************
#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0
#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD
#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U
#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D
#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U
#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D
//*****************************************************************************
//
// PWM_X Generator A/B Control Register action definitions.
//
//*****************************************************************************
#define PWM_GEN_ACT_NONE 0x0 // Do nothing
#define PWM_GEN_ACT_INV 0x1 // Invert the output signal
#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero
#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one
#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action
#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action
#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action
#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action
#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action
#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action
//*****************************************************************************
//
// PWM_X Dead Band Control Register bit definitions.
//
//*****************************************************************************
#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion
//*****************************************************************************
//
// PWM Register reset values.
//
//*****************************************************************************
#define PWM_RV_CTL 0x00000000 // Master control of the PWM module
#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators
#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM
// output pins
#define PWM_RV_INVERT 0x00000000 // Inversion control for
// PWM output pins
#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM
// output pins
#define PWM_RV_INTEN 0x00000000 // Interrupt enable
#define PWM_RV_RIS 0x00000000 // Raw interrupt status
#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing
#define PWM_RV_STATUS 0x00000000 // Status
#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM
// generator block
#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable
#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status
#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing
#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter
#define PWM_RV_X_COUNT 0x00000000 // The current counter value
#define PWM_RV_X_CMPA 0x00000000 // The comparator A value
#define PWM_RV_X_CMPB 0x00000000 // The comparator B value
#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A
#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B
#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator
#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay
// count
#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay
// count
#endif // __HW_PWM_H__

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//*****************************************************************************
//
// hw_qei.h - Macros used when accessing the QEI hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_QEI_H__
#define __HW_QEI_H__
//*****************************************************************************
//
// The following define the offsets of the QEI registers.
//
//*****************************************************************************
#define QEI_O_CTL 0x00000000 // Configuration and control reg.
#define QEI_O_STAT 0x00000004 // Status register
#define QEI_O_POS 0x00000008 // Current position register
#define QEI_O_MAXPOS 0x0000000C // Maximum position register
#define QEI_O_LOAD 0x00000010 // Velocity timer load register
#define QEI_O_TIME 0x00000014 // Velocity timer register
#define QEI_O_COUNT 0x00000018 // Velocity pulse count register
#define QEI_O_SPEED 0x0000001C // Velocity speed register
#define QEI_O_INTEN 0x00000020 // Interrupt enable register
#define QEI_O_RIS 0x00000024 // Raw interrupt status register
#define QEI_O_ISC 0x00000028 // Interrupt status register
//*****************************************************************************
//
// The following define the bit fields in the QEI_CTL register.
//
//*****************************************************************************
#define QEI_CTL_STALLEN 0x00001000 // Stall enable
#define QEI_CTL_INVI 0x00000800 // Invert Index input
#define QEI_CTL_INVB 0x00000400 // Invert PhB input
#define QEI_CTL_INVA 0x00000200 // Invert PhA input
#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask
#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1
#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2
#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4
#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8
#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16
#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32
#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64
#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128
#define QEI_CTL_VELEN 0x00000020 // Velocity enable
#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode
#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode
#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode
#define QEI_CTL_SWAP 0x00000002 // Swap input signals
#define QEI_CTL_ENABLE 0x00000001 // QEI enable
//*****************************************************************************
//
// The following define the bit fields in the QEI_STAT register.
//
//*****************************************************************************
#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation
#define QEI_STAT_ERROR 0x00000001 // Signalling error detected
//*****************************************************************************
//
// The following define the bit fields in the QEI_POS register.
//
//*****************************************************************************
#define QEI_POS_M 0xFFFFFFFF // Current encoder position
#define QEI_POS_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_MAXPOS register.
//
//*****************************************************************************
#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position
#define QEI_MAXPOS_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_LOAD register.
//
//*****************************************************************************
#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value
#define QEI_LOAD_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_TIME register.
//
//*****************************************************************************
#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value
#define QEI_TIME_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_COUNT register.
//
//*****************************************************************************
#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count
#define QEI_COUNT_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_SPEED register.
//
//*****************************************************************************
#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count
#define QEI_SPEED_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_INTEN register.
//
//*****************************************************************************
#define QEI_INTEN_ERROR 0x00000008 // Phase error detected
#define QEI_INTEN_DIR 0x00000004 // Direction change
#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired
#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following define the bit fields in the QEI_RIS register.
//
//*****************************************************************************
#define QEI_RIS_ERROR 0x00000008 // Phase error detected
#define QEI_RIS_DIR 0x00000004 // Direction change
#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired
#define QEI_RIS_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following define the bit fields in the QEI_ISC register.
//
//*****************************************************************************
#define QEI_INT_ERROR 0x00000008 // Phase error detected
#define QEI_INT_DIR 0x00000004 // Direction change
#define QEI_INT_TIMER 0x00000002 // Velocity timer expired
#define QEI_INT_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following define the reset values for the QEI registers.
//
//*****************************************************************************
#define QEI_RV_CTL 0x00000000 // Configuration and control reg.
#define QEI_RV_STAT 0x00000000 // Status register
#define QEI_RV_POS 0x00000000 // Current position register
#define QEI_RV_MAXPOS 0x00000000 // Maximum position register
#define QEI_RV_LOAD 0x00000000 // Velocity timer load register
#define QEI_RV_TIME 0x00000000 // Velocity timer register
#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register
#define QEI_RV_SPEED 0x00000000 // Velocity speed register
#define QEI_RV_INTEN 0x00000000 // Interrupt enable register
#define QEI_RV_RIS 0x00000000 // Raw interrupt status register
#define QEI_RV_ISC 0x00000000 // Interrupt status register
#endif // __HW_QEI_H__

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//*****************************************************************************
//
// hw_ssi.h - Macros used when accessing the SSI hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_SSI_H__
#define __HW_SSI_H__
//*****************************************************************************
//
// The following define the offsets of the SSI registers.
//
//*****************************************************************************
#define SSI_O_CR0 0x00000000 // Control register 0
#define SSI_O_CR1 0x00000004 // Control register 1
#define SSI_O_DR 0x00000008 // Data register
#define SSI_O_SR 0x0000000C // Status register
#define SSI_O_CPSR 0x00000010 // Clock prescale register
#define SSI_O_IM 0x00000014 // Int mask set and clear register
#define SSI_O_RIS 0x00000018 // Raw interrupt register
#define SSI_O_MIS 0x0000001C // Masked interrupt register
#define SSI_O_ICR 0x00000020 // Interrupt clear register
//*****************************************************************************
//
// The following define the bit fields in the SSI Control register 0.
//
//*****************************************************************************
#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase
#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity
#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format
#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format
#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format
#define SSI_CR0_DSS 0x0000000F // Data size select
#define SSI_CR0_DSS_4 0x00000003 // 4 bit data
#define SSI_CR0_DSS_5 0x00000004 // 5 bit data
#define SSI_CR0_DSS_6 0x00000005 // 6 bit data
#define SSI_CR0_DSS_7 0x00000006 // 7 bit data
#define SSI_CR0_DSS_8 0x00000007 // 8 bit data
#define SSI_CR0_DSS_9 0x00000008 // 9 bit data
#define SSI_CR0_DSS_10 0x00000009 // 10 bit data
#define SSI_CR0_DSS_11 0x0000000A // 11 bit data
#define SSI_CR0_DSS_12 0x0000000B // 12 bit data
#define SSI_CR0_DSS_13 0x0000000C // 13 bit data
#define SSI_CR0_DSS_14 0x0000000D // 14 bit data
#define SSI_CR0_DSS_15 0x0000000E // 15 bit data
#define SSI_CR0_DSS_16 0x0000000F // 16 bit data
//*****************************************************************************
//
// The following define the bit fields in the SSI Control register 1.
//
//*****************************************************************************
#define SSI_CR1_SOD 0x00000008 // Slave mode output disable
#define SSI_CR1_MS 0x00000004 // Master or slave mode select
#define SSI_CR1_SSE 0x00000002 // Sync serial port enable
#define SSI_CR1_LBM 0x00000001 // Loopback mode
//*****************************************************************************
//
// The following define the bit fields in the SSI Status register.
//
//*****************************************************************************
#define SSI_SR_BSY 0x00000010 // SSI busy
#define SSI_SR_RFF 0x00000008 // RX FIFO full
#define SSI_SR_RNE 0x00000004 // RX FIFO not empty
#define SSI_SR_TNF 0x00000002 // TX FIFO not full
#define SSI_SR_TFE 0x00000001 // TX FIFO empty
//*****************************************************************************
//
// The following define the bit fields in the SSI clock prescale register.
//
//*****************************************************************************
#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
//*****************************************************************************
//
// The following define information concerning the SSI Data register.
//
//*****************************************************************************
#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
//*****************************************************************************
//
// The following define the bit fields in the interrupt mask set and clear,
// raw interrupt, masked interrupt, and interrupt clear registers.
//
//*****************************************************************************
#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
#endif // __HW_SSI_H__

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//*****************************************************************************
//
// hw_timer.h - Defines and macros used when accessing the timer.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_TIMER_H__
#define __HW_TIMER_H__
//*****************************************************************************
//
// The following define the offsets of the timer registers.
//
//*****************************************************************************
#define TIMER_O_CFG 0x00000000 // Configuration register
#define TIMER_O_TAMR 0x00000004 // TimerA mode register
#define TIMER_O_TBMR 0x00000008 // TimerB mode register
#define TIMER_O_CTL 0x0000000C // Control register
#define TIMER_O_IMR 0x00000018 // Interrupt mask register
#define TIMER_O_RIS 0x0000001C // Interrupt status register
#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.
#define TIMER_O_ICR 0x00000024 // Interrupt clear register
#define TIMER_O_TAILR 0x00000028 // TimerA interval load register
#define TIMER_O_TBILR 0x0000002C // TimerB interval load register
#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register
#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register
#define TIMER_O_TAPR 0x00000038 // TimerA prescale register
#define TIMER_O_TBPR 0x0000003C // TimerB prescale register
#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register
#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register
#define TIMER_O_TAR 0x00000048 // TimerA register
#define TIMER_O_TBR 0x0000004C // TimerB register
//*****************************************************************************
//
// The following define the reset values of the timer registers.
//
//*****************************************************************************
#define TIMER_RV_CFG 0x00000000 // Configuration register RV
#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
#define TIMER_RV_CTL 0x00000000 // Control register RV
#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
//*****************************************************************************
//
// The following define the bit fields in the TIMER_CFG register.
//
//*****************************************************************************
#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TnMR register.
//
//*****************************************************************************
#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
//*****************************************************************************
//
// The following define the bit fields in the TIMER_CTL register.
//
//*****************************************************************************
#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert
#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable
#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge
#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge
#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable
#define TIMER_CTL_TBEN 0x00000100 // TimerB enable
#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert
#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable
#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable
#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge
#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge
#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable
#define TIMER_CTL_TAEN 0x00000001 // TimerA enable
//*****************************************************************************
//
// The following define the bit fields in the TIMER_IMR register.
//
//*****************************************************************************
#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask
#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask
#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask
#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask
#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask
#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask
#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask
//*****************************************************************************
//
// The following define the bit fields in the TIMER_RIS register.
//
//*****************************************************************************
#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status
#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status
#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status
#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status
#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status
#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status
#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status
//*****************************************************************************
//
// The following define the bit fields in the TIMER_MIS register.
//
//*****************************************************************************
#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
//*****************************************************************************
//
// The following define the bit fields in the TIMER_ICR register.
//
//*****************************************************************************
#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear
#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear
#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear
#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear
#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear
#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear
#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TAILR register.
//
//*****************************************************************************
#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TBILR register.
//
//*****************************************************************************
#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TAMATCHR register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TBMATCHR register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TnPR register.
//
//*****************************************************************************
#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TnPMR register.
//
//*****************************************************************************
#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TAR register.
//
//*****************************************************************************
#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TBR register.
//
//*****************************************************************************
#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
#endif // __HW_TIMER_H__

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//*****************************************************************************
//
// hw_types.h - Common types and macros.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_TYPES_H__
#define __HW_TYPES_H__
//*****************************************************************************
//
// Define a boolean type, and values for true and false.
//
//*****************************************************************************
typedef unsigned char tBoolean;
#ifndef true
#define true 1
#endif
#ifndef false
#define false 0
#endif
//*****************************************************************************
//
// Macros for hardware access, both direct and via the bit-band region.
//
//*****************************************************************************
#define HWREG(x) \
(*((volatile unsigned long *)(x)))
#define HWREGH(x) \
(*((volatile unsigned short *)(x)))
#define HWREGB(x) \
(*((volatile unsigned char *)(x)))
#define HWREGBITW(x, b) \
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITH(x, b) \
HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITB(x, b) \
HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#endif // __HW_TYPES_H__

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//*****************************************************************************
//
// hw_uart.h - Macros and defines used when accessing the UART hardware
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_UART_H__
#define __HW_UART_H__
//*****************************************************************************
//
// UART Register Offsets.
//
//*****************************************************************************
#define UART_O_DR 0x00000000 // Data Register
#define UART_O_RSR 0x00000004 // Receive Status Register (read)
#define UART_O_ECR 0x00000004 // Error Clear Register (write)
#define UART_O_FR 0x00000018 // Flag Register (read only)
#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg
#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg
#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte
#define UART_O_CTL 0x00000030 // Control Register
#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg
#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg
#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register
#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register
#define UART_O_ICR 0x00000044 // Interrupt Clear Register
#define UART_O_PeriphID4 0x00000FD0 //
#define UART_O_PeriphID5 0x00000FD4 //
#define UART_O_PeriphID6 0x00000FD8 //
#define UART_O_PeriphID7 0x00000FDC //
#define UART_O_PeriphID0 0x00000FE0 //
#define UART_O_PeriphID1 0x00000FE4 //
#define UART_O_PeriphID2 0x00000FE8 //
#define UART_O_PeriphID3 0x00000FEC //
#define UART_O_PCellID0 0x00000FF0 //
#define UART_O_PCellID1 0x00000FF4 //
#define UART_O_PCellID2 0x00000FF8 //
#define UART_O_PCellID3 0x00000FFC //
//*****************************************************************************
//
// Data Register bits
//
//*****************************************************************************
#define UART_DR_OE 0x00000800 // Overrun Error
#define UART_DR_BE 0x00000400 // Break Error
#define UART_DR_PE 0x00000200 // Parity Error
#define UART_DR_FE 0x00000100 // Framing Error
#define UART_DR_DATA_MASK 0x000000FF // UART data
//*****************************************************************************
//
// Receive Status Register bits
//
//*****************************************************************************
#define UART_RSR_OE 0x00000008 // Overrun Error
#define UART_RSR_BE 0x00000004 // Break Error
#define UART_RSR_PE 0x00000002 // Parity Error
#define UART_RSR_FE 0x00000001 // Framing Error
//*****************************************************************************
//
// Flag Register bits
//
//*****************************************************************************
#define UART_FR_TXFE 0x00000080 // TX FIFO Empty
#define UART_FR_RXFF 0x00000040 // RX FIFO Full
#define UART_FR_TXFF 0x00000020 // TX FIFO Full
#define UART_FR_RXFE 0x00000010 // RX FIFO Empty
#define UART_FR_BUSY 0x00000008 // UART Busy
//*****************************************************************************
//
// Integer baud-rate divisor
//
//*****************************************************************************
#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor
//*****************************************************************************
//
// Fractional baud-rate divisor
//
//*****************************************************************************
#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor
//*****************************************************************************
//
// Line Control Register High bits
//
//*****************************************************************************
#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select
#define UART_LCR_H_WLEN 0x00000060 // Word length
#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data
#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data
#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data
#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data
#define UART_LCR_H_FEN 0x00000010 // Enable FIFO
#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select
#define UART_LCR_H_EPS 0x00000004 // Even Parity Select
#define UART_LCR_H_PEN 0x00000002 // Parity Enable
#define UART_LCR_H_BRK 0x00000001 // Send Break
//*****************************************************************************
//
// Control Register bits
//
//*****************************************************************************
#define UART_CTL_RXE 0x00000200 // Receive Enable
#define UART_CTL_TXE 0x00000100 // Transmit Enable
#define UART_CTL_LBE 0x00000080 // Loopback Enable
#define UART_CTL_UARTEN 0x00000001 // UART Enable
//*****************************************************************************
//
// Interrupt FIFO Level Select Register bits
//
//*****************************************************************************
#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full
#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full
#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full
#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full
#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full
#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full
#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full
#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full
#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full
#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full
//*****************************************************************************
//
// Interrupt Mask Set/Clear Register bits
//
//*****************************************************************************
#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask
#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask
#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask
#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask
#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask
#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask
#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask
//*****************************************************************************
//
// Raw Interrupt Status Register
//
//*****************************************************************************
#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status
#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status
#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status
#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status
#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status
#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status
#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status
//*****************************************************************************
//
// Masked Interrupt Status Register
//
//*****************************************************************************
#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status
#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status
#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status
#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status
#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status
#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status
#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status
//*****************************************************************************
//
// Interrupt Clear Register bits
//
//*****************************************************************************
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
#define UART_RSR_ANY (UART_RSR_OE | \
UART_RSR_BE | \
UART_RSR_PE | \
UART_RSR_FE)
//*****************************************************************************
//
// Reset Values for UART Registers.
//
//*****************************************************************************
#define UART_RV_DR 0x00000000
#define UART_RV_RSR 0x00000000
#define UART_RV_ECR 0x00000000
#define UART_RV_FR 0x00000090
#define UART_RV_IBRD 0x00000000
#define UART_RV_FBRD 0x00000000
#define UART_RV_LCR_H 0x00000000
#define UART_RV_CTL 0x00000300
#define UART_RV_IFLS 0x00000012
#define UART_RV_IM 0x00000000
#define UART_RV_RIS 0x00000000
#define UART_RV_MIS 0x00000000
#define UART_RV_ICR 0x00000000
#define UART_RV_PeriphID4 0x00000000
#define UART_RV_PeriphID5 0x00000000
#define UART_RV_PeriphID6 0x00000000
#define UART_RV_PeriphID7 0x00000000
#define UART_RV_PeriphID0 0x00000011
#define UART_RV_PeriphID1 0x00000000
#define UART_RV_PeriphID2 0x00000018
#define UART_RV_PeriphID3 0x00000001
#define UART_RV_PCellID0 0x0000000D
#define UART_RV_PCellID1 0x000000F0
#define UART_RV_PCellID2 0x00000005
#define UART_RV_PCellID3 0x000000B1
#endif // __HW_UART_H__

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//*****************************************************************************
//
// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_WATCHDOG_H__
#define __HW_WATCHDOG_H__
//*****************************************************************************
//
// The following define the offsets of the Watchdog Timer registers.
//
//*****************************************************************************
#define WDT_O_LOAD 0x00000000 // Load register
#define WDT_O_VALUE 0x00000004 // Current value register
#define WDT_O_CTL 0x00000008 // Control register
#define WDT_O_ICR 0x0000000C // Interrupt clear register
#define WDT_O_RIS 0x00000010 // Raw interrupt status register
#define WDT_O_MIS 0x00000014 // Masked interrupt status register
#define WDT_O_TEST 0x00000418 // Test register
#define WDT_O_LOCK 0x00000C00 // Lock register
#define WDT_O_PeriphID4 0x00000FD0 //
#define WDT_O_PeriphID5 0x00000FD4 //
#define WDT_O_PeriphID6 0x00000FD8 //
#define WDT_O_PeriphID7 0x00000FDC //
#define WDT_O_PeriphID0 0x00000FE0 //
#define WDT_O_PeriphID1 0x00000FE4 //
#define WDT_O_PeriphID2 0x00000FE8 //
#define WDT_O_PeriphID3 0x00000FEC //
#define WDT_O_PCellID0 0x00000FF0 //
#define WDT_O_PCellID1 0x00000FF4 //
#define WDT_O_PCellID2 0x00000FF8 //
#define WDT_O_PCellID3 0x00000FFC //
//*****************************************************************************
//
// The following define the bit fields in the WDT_CTL register.
//
//*****************************************************************************
#define WDT_CTL_RESEN 0x00000002 // Enable reset output
#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int
//*****************************************************************************
//
// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS
// registers.
//
//*****************************************************************************
#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
//*****************************************************************************
//
// The following define the bit fields in the WDT_TEST register.
//
//*****************************************************************************
#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable
#ifndef DEPRECATED
#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
#endif
//*****************************************************************************
//
// The following define the bit fields in the WDT_LOCK register.
//
//*****************************************************************************
#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked
#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked
#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
//*****************************************************************************
//
// The following define the reset values for the WDT registers.
//
//*****************************************************************************
#define WDT_RV_LOAD 0xFFFFFFFF // Load register
#define WDT_RV_VALUE 0xFFFFFFFF // Current value register
#define WDT_RV_CTL 0x00000000 // Control register
#define WDT_RV_RIS 0x00000000 // Raw interrupt status register
#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
#define WDT_RV_LOCK 0x00000000 // Lock register
#define WDT_RV_PeriphID4 0x00000000 //
#define WDT_RV_PeriphID5 0x00000000 //
#define WDT_RV_PeriphID6 0x00000000 //
#define WDT_RV_PeriphID7 0x00000000 //
#define WDT_RV_PeriphID0 0x00000005 //
#define WDT_RV_PeriphID1 0x00000018 //
#define WDT_RV_PeriphID2 0x00000018 //
#define WDT_RV_PeriphID3 0x00000001 //
#define WDT_RV_PCellID0 0x0000000D //
#define WDT_RV_PCellID1 0x000000F0 //
#define WDT_RV_PCellID2 0x00000005 //
#define WDT_RV_PCellID3 0x000000B1 //
#endif // __HW_WATCHDOG_H__

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//*****************************************************************************
//
// osram96x16.h - Prototypes for the driver for the OSRAM 96x16 graphical OLED
// display.
//
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __OSRAM96X16_H__
#define __OSRAM96X16_H__
//*****************************************************************************
//
// Prototypes for the driver APIs.
//
//*****************************************************************************
extern void OSRAMClear(void);
extern void OSRAMStringDraw(const char *pcStr, unsigned long ulX,
unsigned long ulY);
extern void OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX,
unsigned long ulY, unsigned long ulWidth,
unsigned long ulHeight);
extern void OSRAMInit(tBoolean bFast);
extern void OSRAMDisplayOn(void);
extern void OSRAMDisplayOff(void);
#endif // __OSRAM96X16_H__

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//*****************************************************************************
//
// adc.h - ADC headers for using the ADC driver functions.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __ADC_H__
#define __ADC_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ADCSequenceConfigure as the ulTrigger
// parameter.
//
//*****************************************************************************
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
//*****************************************************************************
//
// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
// parameter.
//
//*****************************************************************************
#define ADC_CTL_TS 0x00000080 // Temperature sensor select
#define ADC_CTL_IE 0x00000040 // Interrupt enable
#define ADC_CTL_END 0x00000020 // Sequence end select
#define ADC_CTL_D 0x00000010 // Differential select
#define ADC_CTL_CH0 0x00000000 // Input channel 0
#define ADC_CTL_CH1 0x00000001 // Input channel 1
#define ADC_CTL_CH2 0x00000002 // Input channel 2
#define ADC_CTL_CH3 0x00000003 // Input channel 3
#define ADC_CTL_CH4 0x00000004 // Input channel 4
#define ADC_CTL_CH5 0x00000005 // Input channel 5
#define ADC_CTL_CH6 0x00000006 // Input channel 6
#define ADC_CTL_CH7 0x00000007 // Input channel 7
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
void (*pfnHandler)(void));
extern void ADCIntUnregister(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
extern unsigned long ADCIntStatus(unsigned long ulBase,
unsigned long ulSequenceNum,
tBoolean bMasked);
extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCSequenceEnable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceDisable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulTrigger,
unsigned long ulPriority);
extern void ADCSequenceStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern long ADCSequenceOverflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceUnderflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer);
extern void ADCProcessorTrigger(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulFactor);
extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer,
unsigned long ulCount);
#ifdef __cplusplus
}
#endif
#endif // __ADC_H__

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//*****************************************************************************
//
// comp.h - Prototypes for the analog comparator driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __COMP_H__
#define __COMP_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ComparatorConfigure() as the ulConfig
// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of
// the values may be selected and ORed together will values from the other
// groups.
//
//*****************************************************************************
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
#define COMP_TRIG_LOW 0x00000800 // Trigger when low
#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
#define COMP_INT_HIGH 0x00000010 // Interrupt when high
#define COMP_INT_LOW 0x00000000 // Interrupt when low
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_OUTPUT_NONE 0x00000000 // No comparator output
#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal
#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted
//*****************************************************************************
//
// Values that can be passed to ComparatorSetRef() as the ulRef parameter.
//
//*****************************************************************************
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
#define COMP_REF_0V 0x00000300 // Internal reference of 0V
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig);
extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);
extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
void (*pfnHandler)(void));
extern void ComparatorIntUnregister(unsigned long ulBase,
unsigned long ulComp);
extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);
extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
tBoolean bMasked);
extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);
#ifdef __cplusplus
}
#endif
#endif // __COMP_H__

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//*****************************************************************************
//
// cpu.h - Prototypes for the CPU instruction wrapper functions.
//
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __CPU_H__
#define __CPU_H__
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern void CPUcpsid(void);
extern void CPUcpsie(void);
extern void CPUwfi(void);
#endif // __CPU_H__

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//*****************************************************************************
//
// debug.h - Macros for assisting debug of the driver library.
//
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __DEBUG_H__
#define __DEBUG_H__
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build.
//
//*****************************************************************************
extern void __error__(char *pcFilename, unsigned long ulLine);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#define ASSERT(expr) { \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
}
#else
#define ASSERT(expr)
#endif
#endif // __DEBUG_H__

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//*****************************************************************************
//
// flash.h - Prototypes for the flash driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __FLASH_H__
#define __FLASH_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FlashProtectSet(), and returned by
// FlashProtectGet().
//
//*****************************************************************************
typedef enum
{
FlashReadWrite, // Flash can be read and written
FlashReadOnly, // Flash can only be read
FlashExecuteOnly // Flash can only be executed
}
tFlashProtection;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long FlashUsecGet(void);
extern void FlashUsecSet(unsigned long ulClocks);
extern long FlashErase(unsigned long ulAddress);
extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount);
extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
extern long FlashProtectSet(unsigned long ulAddress,
tFlashProtection eProtect);
extern long FlashProtectSave(void);
extern void FlashIntRegister(void (*pfnHandler)(void));
extern void FlashIntUnregister(void);
extern void FlashIntEnable(unsigned long ulIntFlags);
extern void FlashIntDisable(unsigned long ulIntFlags);
extern unsigned long FlashIntGetStatus(tBoolean bMasked);
extern void FlashIntClear(unsigned long ulIntFlags);
#ifdef __cplusplus
}
#endif
#endif // __FLASH_H__

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//*****************************************************************************
//
// gpio.h - Defines and Macros for GPIO API.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following values define the bit field for the ucPins argument to several
// of the APIs.
//
//*****************************************************************************
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
//*****************************************************************************
//
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
// returned from GPIODirModeGet.
//
//*****************************************************************************
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
//*****************************************************************************
//
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
// returned from GPIOIntTypeGet.
//
//*****************************************************************************
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
// and returned by GPIOPadConfigGet in the *pulStrength parameter.
//
//*****************************************************************************
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
// and returned by GPIOPadConfigGet in the *pulPadType parameter.
//
//*****************************************************************************
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO);
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType);
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulStrength,
unsigned long ulPadType);
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
unsigned long *pulStrength,
unsigned long *pulPadType);
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPortIntRegister(unsigned long ulPort,
void (*pfIntHandler)(void));
extern void GPIOPortIntUnregister(unsigned long ulPort);
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
unsigned char ucVal);
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
#ifdef __cplusplus
}
#endif
#endif // __GPIO_H__

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//*****************************************************************************
//
// i2c.h - Prototypes for the I2C Driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __I2C_H__
#define __I2C_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// Interrupt defines.
//
//*****************************************************************************
#define I2C_INT_MASTER 0x00000001
#define I2C_INT_SLAVE 0x00000002
//*****************************************************************************
//
// I2C Master commands.
//
//*****************************************************************************
#define I2C_MASTER_CMD_SINGLE_SEND \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_SINGLE_RECEIVE \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_START \
(I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_CONT \
(I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
(I2C_MASTER_CS_STOP)
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
(I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
(I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)
//*****************************************************************************
//
// I2C Master error status.
//
//*****************************************************************************
#define I2C_MASTER_ERR_NONE 0
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
//*****************************************************************************
//
// I2C Slave action requests
//
//*****************************************************************************
#define I2C_SLAVE_ACT_NONE 0
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
//*****************************************************************************
// Miscellaneous I2C driver definitions.
//*****************************************************************************
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));
extern void I2CIntUnregister(unsigned long ulBase);
extern tBoolean I2CMasterBusBusy(unsigned long ulBase);
extern tBoolean I2CMasterBusy(unsigned long ulBase);
extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);
extern unsigned long I2CMasterDataGet(unsigned long ulBase);
extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CMasterDisable(unsigned long ulBase);
extern void I2CMasterEnable(unsigned long ulBase);
extern unsigned long I2CMasterErr(unsigned long ulBase);
extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast);
extern void I2CMasterIntClear(unsigned long ulBase);
extern void I2CMasterIntDisable(unsigned long ulBase);
extern void I2CMasterIntEnable(unsigned long ulBase);
extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
unsigned char ucSlaveAddr,
tBoolean bReceive);
extern unsigned long I2CSlaveDataGet(unsigned long ulBase);
extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CSlaveDisable(unsigned long ulBase);
extern void I2CSlaveEnable(unsigned long ulBase);
extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
extern void I2CSlaveIntClear(unsigned long ulBase);
extern void I2CSlaveIntDisable(unsigned long ulBase);
extern void I2CSlaveIntEnable(unsigned long ulBase);
extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);
extern unsigned long I2CSlaveStatus(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __I2C_H__

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//*****************************************************************************
//
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void IntMasterEnable(void);
extern void IntMasterDisable(void);
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
extern void IntUnregister(unsigned long ulInterrupt);
extern void IntPriorityGroupingSet(unsigned long ulBits);
extern unsigned long IntPriorityGroupingGet(void);
extern void IntPrioritySet(unsigned long ulInterrupt,
unsigned char ucPriority);
extern long IntPriorityGet(unsigned long ulInterrupt);
extern void IntEnable(unsigned long ulInterrupt);
extern void IntDisable(unsigned long ulInterrupt);
#ifdef __cplusplus
}
#endif
#endif // __INTERRUPT_H__

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//*****************************************************************************
//
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __PWM_H__
#define __PWM_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are passed to PWMGenConfigure() as the ulConfig
// parameter and specify the configuration of the PWM generator.
//
//*****************************************************************************
#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM generator interrupts and
// triggers.
//
//*****************************************************************************
#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM interrupts.
//
//*****************************************************************************
#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
#define PWM_INT_FAULT 0x00010000 // Fault interrupt
//*****************************************************************************
//
// Defines to identify the generators within a module.
//
//*****************************************************************************
#define PWM_GEN_0 0x00000040 // Offset address of Gen0
#define PWM_GEN_1 0x00000080 // Offset address of Gen1
#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
//*****************************************************************************
//
// Defines to identify the outputs within a module.
//
//*****************************************************************************
#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
unsigned long ulConfig);
extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
unsigned long ulPeriod);
extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
unsigned long ulGen);
extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
unsigned long ulWidth);
extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
unsigned long ulPWMOut);
extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
unsigned short usRise, unsigned short usFall);
extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bEnable);
extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bInvert);
extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bFaultKill);
extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
void (*pfIntHandler)(void));
extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
extern void PWMFaultIntRegister(unsigned long ulBase,
void (*pfIntHandler)(void));
extern void PWMFaultIntUnregister(unsigned long ulBase);
extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
tBoolean bMasked);
extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
unsigned long ulInts);
extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMFaultIntClear(unsigned long ulBase);
extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
#ifdef __cplusplus
}
#endif
#endif // __PWM_H__

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//*****************************************************************************
//
// qei.h - Prototypes for the Quadrature Encoder Driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __QEI_H__
#define __QEI_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to QEIConfigure as the ulConfig paramater.
//
//*****************************************************************************
#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only
#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges
#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse
#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse
#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature
#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir
#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB
#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB
//*****************************************************************************
//
// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.
//
//*****************************************************************************
#define QEI_VELDIV_1 0x00000000 // Predivide by 1
#define QEI_VELDIV_2 0x00000040 // Predivide by 2
#define QEI_VELDIV_4 0x00000080 // Predivide by 4
#define QEI_VELDIV_8 0x000000C0 // Predivide by 8
#define QEI_VELDIV_16 0x00000100 // Predivide by 16
#define QEI_VELDIV_32 0x00000140 // Predivide by 32
#define QEI_VELDIV_64 0x00000180 // Predivide by 64
#define QEI_VELDIV_128 0x000001C0 // Predivide by 128
//*****************************************************************************
//
// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts
// as the ulIntFlags parameter, and returned by QEIGetIntStatus.
//
//*****************************************************************************
#define QEI_INTERROR 0x00000008 // Phase error detected
#define QEI_INTDIR 0x00000004 // Direction change
#define QEI_INTTIMER 0x00000002 // Velocity timer expired
#define QEI_INTINDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void QEIEnable(unsigned long ulBase);
extern void QEIDisable(unsigned long ulBase);
extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxPosition);
extern unsigned long QEIPositionGet(unsigned long ulBase);
extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);
extern long QEIDirectionGet(unsigned long ulBase);
extern tBoolean QEIErrorGet(unsigned long ulBase);
extern void QEIVelocityEnable(unsigned long ulBase);
extern void QEIVelocityDisable(unsigned long ulBase);
extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
unsigned long ulPeriod);
extern unsigned long QEIVelocityGet(unsigned long ulBase);
extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void QEIIntUnregister(unsigned long ulBase);
extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
#ifdef __cplusplus
}
#endif
#endif // __QEI_H__

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