Added back some TCP/IP stack port layer files.

FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/stm32f2xx_hal_eth.h

@@ -0,0 +1,6 @@
+/*
+ * The Ethernet header files for STM32F2, STM32F4 and STM32F7 have been merged to
+ * a single module that works for both parts: "stm32fxx_hal_eth"
+ */
+
+#include "stm32fxx_hal_eth.h"

FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/stm32f4xx_hal_eth.h

@@ -0,0 +1,6 @@
+/*
+ * The Ethernet header files for STM32F2, STM32F4 and STM32F7 have been merged to
+ * a single module that works for both parts: "stm32fxx_hal_eth"
+ */
+
+#include "stm32fxx_hal_eth.h"

FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/stm32f7xx_hal_eth.h

@@ -0,0 +1,6 @@
+/*
+ * The Ethernet header files for STM32F2, STM32F4 and STM32F7 have been merged to
+ * a single module that works for both parts: "stm32fxx_hal_eth"
+ */
+
+#include "stm32fxx_hal_eth.h"

FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/uncached_memory.c

@@ -0,0 +1,132 @@
+/*
+ * uncached_memory.c
+ *
+ * This module will declare 1 MB of memory and switch off the caching for it.
+ *
+ * pucGetUncachedMemory( ulSize ) returns a trunc of this memory with a length
+ * rounded up to a multiple of 4 KB
+ *
+ * ucIsCachedMemory( pucBuffer ) returns non-zero if a given pointer is NOT
+ * within the range of the 1 MB non-cached memory.
+ *
+ */
+
+/*
+ * After "_end", 1 MB of uncached memory will be allocated for DMA transfers.
+ * Both the DMA descriptors as well as all EMAC TX-buffers will be allocated in
+ * uncached memory.
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* FreeRTOS+TCP includes. */
+#include "FreeRTOS_IP.h"
+#include "FreeRTOS_Sockets.h"
+#include "FreeRTOS_IP_Private.h"
+
+#include "Zynq/x_emacpsif.h"
+#include "Zynq/x_topology.h"
+#include "xstatus.h"
+
+#include "xparameters.h"
+#include "xparameters_ps.h"
+#include "xil_exception.h"
+#include "xil_mmu.h"
+
+#include "uncached_memory.h"
+
+#define UNCACHED_MEMORY_SIZE	0x100000ul
+
+#define DDR_MEMORY_END	(XPAR_PS7_DDR_0_S_AXI_HIGHADDR+1)
+
+static void vInitialiseUncachedMemory( void );
+
+static uint8_t *pucHeadOfMemory;
+static uint32_t ulMemorySize;
+static uint8_t *pucStartOfMemory = NULL;
+
+uint8_t ucIsCachedMemory( const uint8_t *pucBuffer )
+{
+uint8_t ucReturn;
+
+	if( ( pucStartOfMemory != NULL ) &&
+		( pucBuffer >= pucStartOfMemory ) &&
+		( pucBuffer < ( pucStartOfMemory + UNCACHED_MEMORY_SIZE ) ) )
+	{
+		ucReturn = pdFALSE;
+	}
+	else
+	{
+		ucReturn = pdTRUE;
+	}
+
+	return ucReturn;
+}
+
+uint8_t *pucGetUncachedMemory( uint32_t ulSize )
+{
+uint8_t *pucReturn;
+
+	if( pucStartOfMemory == NULL )
+	{
+		vInitialiseUncachedMemory( );
+	}
+	if( ( pucStartOfMemory == NULL ) || ( ulSize > ulMemorySize ) )
+	{
+		pucReturn = NULL;
+	}
+	else
+	{
+	uint32_t ulSkipSize;
+
+		pucReturn = pucHeadOfMemory;
+		ulSkipSize = ( ulSize + 0x1000ul ) & ~0xffful;
+		pucHeadOfMemory += ulSkipSize;
+		ulMemorySize -= ulSkipSize;
+	}
+
+	return pucReturn;
+}
+
+extern u8 _end;
+
+static void vInitialiseUncachedMemory( )
+{
+	/* At the end of program's space... */
+	pucStartOfMemory = (uint8_t *) &_end;
+	/*
+	 * Align the start address to 1 MB boundary.
+	 */
+	pucStartOfMemory = (uint8_t *)( ( ( uint32_t )pucStartOfMemory + UNCACHED_MEMORY_SIZE ) & ( ~( UNCACHED_MEMORY_SIZE - 1 ) ) );
+
+	if( ( ( u32 )pucStartOfMemory ) + UNCACHED_MEMORY_SIZE > DDR_MEMORY_END )
+	{
+//		vLoggingPrintf("vInitialiseUncachedMemory: Can not allocate uncached memory\n" );
+	}
+	else
+	{
+		/*
+		 * Some objects want to be stored in uncached memory. Hence the 1 MB
+		 * address range that starts after "_end" is made uncached
+		 * by setting appropriate attributes in the translation table.
+		 */
+		/* FIXME claudio rossi. Modified to prevent data abort exception (misaligned access)
+		 * when application is compiled with -O1 or more optimization flag.
+		 */
+/*		Xil_SetTlbAttributes( ( uint32_t )pucStartOfMemory, 0xc02 ); // addr, attr */
+		Xil_SetTlbAttributes( ( uint32_t )pucStartOfMemory, 0x1c02 ); // addr, attr
+
+		/* For experiments in the SDIO driver, make the remaining uncached memory public */
+		pucHeadOfMemory = pucStartOfMemory;
+		ulMemorySize = UNCACHED_MEMORY_SIZE;
+		memset( pucStartOfMemory, '\0', UNCACHED_MEMORY_SIZE );
+	}
+}

FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/uncached_memory.h

@@ -0,0 +1,23 @@
+/*
+ * uncached_memory.h
+ *
+ * This module will declare 1 MB of memory and switch off the caching for it.
+ *
+ * pucGetUncachedMemory( ulSize ) returns a trunc of this memory with a length
+ * rounded up to a multiple of 4 KB
+ *
+ * ucIsCachedMemory( pucBuffer ) returns non-zero if a given pointer is NOT
+ * within the range of the 1 MB non-cached memory.
+ *
+ */
+
+#ifndef UNCACHEMEMORY_H
+
+#define UNCACHEMEMORY_H
+
+uint8_t *pucGetUncachedMemory( uint32_t ulSize );
+
+uint8_t ucIsCachedMemory( const uint8_t *pucBuffer );
+
+#endif /* UNCACHEMEMORY_H */
+

FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/include/phyHandling.h

@@ -0,0 +1,118 @@
+/*
+ * Handling of Ethernet PHY's
+ * PHY's communicate with an EMAC either through
+ * a Media-Independent Interface (MII), or a Reduced Media-Independent Interface (RMII).
+ * The EMAC can poll for PHY ports on 32 different addresses. Each of the PHY ports
+ * shall be treated independently.
+ * 
+ */
+
+#ifndef PHYHANDLING_H
+
+#define PHYHANDLING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifndef ipconfigPHY_MAX_PORTS
+	/* There can be at most 32 PHY ports, but in most cases there are 4 or less. */
+	#define	ipconfigPHY_MAX_PORTS	4
+#endif
+
+/* A generic user-provided function that reads from the PHY-port at 'xAddress'( 0-based ). A 16-bit value shall be stored in
+  '*pulValue'. xRegister is the register number ( 0 .. 31 ). In fact all PHY registers are 16-bit.
+  Return non-zero in case the action failed. */
+typedef BaseType_t ( *xApplicationPhyReadHook_t )( BaseType_t xAddress, BaseType_t xRegister, uint32_t *pulValue );
+
+/* A generic user-provided function that writes 'ulValue' to the
+   PHY-port at 'xAddress' ( 0-based ). xRegister is the register number ( 0 .. 31 ).
+   Return non-zero in case the action failed. */
+typedef BaseType_t ( *xApplicationPhyWriteHook_t )( BaseType_t xAddress, BaseType_t xRegister, uint32_t ulValue );
+
+typedef struct xPhyProperties
+{
+	uint8_t ucSpeed;
+	uint8_t ucMDI_X;		/* MDI-X : Medium Dependent Interface - Crossover */
+	uint8_t ucDuplex;
+	uint8_t ucSpare;
+} PhyProperties_t;
+
+typedef struct xEthernetPhy
+{
+	xApplicationPhyReadHook_t fnPhyRead;
+	xApplicationPhyWriteHook_t fnPhyWrite;
+	uint32_t ulPhyIDs[ ipconfigPHY_MAX_PORTS ];
+	uint8_t ucPhyIndexes[ ipconfigPHY_MAX_PORTS ];
+	TimeOut_t xLinkStatusTimer;
+	TickType_t xLinkStatusRemaining;
+	BaseType_t xPortCount;
+	uint32_t ulBCRValue;
+	uint32_t ulACRValue;
+	uint32_t ulLinkStatusMask;
+	PhyProperties_t xPhyPreferences;
+	PhyProperties_t xPhyProperties;
+} EthernetPhy_t;
+
+/* Some defines used internally here to indicate preferences about speed, MDIX
+(wired direct or crossed), and duplex (half or full). */
+
+/* Values for PhyProperties_t::ucSpeed : */
+#define	PHY_SPEED_10		1
+#define	PHY_SPEED_100		2
+#define	PHY_SPEED_AUTO		3
+
+/* Values for PhyProperties_t::ucMDI_X : */
+#define	PHY_MDIX_DIRECT		1
+#define	PHY_MDIX_CROSSED	2
+#define	PHY_MDIX_AUTO		3
+
+/* Values for PhyProperties_t::ucDuplex : */
+#define	PHY_DUPLEX_HALF		1
+#define	PHY_DUPLEX_FULL		2
+#define	PHY_DUPLEX_AUTO		3
+
+/* ID's of supported PHY's : */
+#define PHY_ID_LAN8742A		0x0007c130
+#define PHY_ID_LAN8720		0x0007c0f0
+
+#define PHY_ID_KSZ8041		0x000010A1
+#define PHY_ID_KSZ8051		0x000010A1
+#define PHY_ID_KSZ8081		0x000010A1
+
+#define PHY_ID_KSZ8863		0x00221430
+#define PHY_ID_KSZ8081MNXIA 0x00221560
+
+#define PHY_ID_DP83848I		0x20005C90
+
+
+/* Initialise the struct and assign a PHY-read and -write function. */
+void vPhyInitialise( EthernetPhy_t *pxPhyObject, xApplicationPhyReadHook_t fnPhyRead, xApplicationPhyWriteHook_t fnPhyWrite );
+
+/* Discover all PHY's connected by polling 32 indexes ( zero-based ) */
+BaseType_t xPhyDiscover( EthernetPhy_t *pxPhyObject );
+
+/* Send a reset command to the connected PHY ports and send configuration. */
+BaseType_t xPhyConfigure( EthernetPhy_t *pxPhyObject, const PhyProperties_t *pxPhyProperties );
+
+/* Give a command to start auto negotiation on a set of PHY port's. */
+BaseType_t xPhyStartAutoNegotiation( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask );
+
+/* Do not use auto negotiation but use predefined values from 'pxPhyObject->xPhyPreferences'. */
+BaseType_t xPhyFixedValue( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask );
+
+/* Check the current Link Status.
+'xHadReception' : make this true if a packet has been received since the
+last call to this function. */
+BaseType_t xPhyCheckLinkStatus( EthernetPhy_t *pxPhyObject, BaseType_t xHadReception );
+
+/* Get the bitmask of a given 'EthernetPhy_t'. */
+#define xPhyGetMask( pxPhyObject ) \
+	( ( ( ( uint32_t ) 1u ) << ( pxPhyObject )->xPortCount ) - 1u )
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif

FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/ksz8851snl.h

@@ -0,0 +1,67 @@
+/**
+ *
+ * \file
+ *
+ * \brief KS8851SNL driver for SAM.
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef KSZ8851SNL_H_INCLUDED
+#define KSZ8851SNL_H_INCLUDED
+
+#include "gpio.h"
+
+void configure_intn(void (*p_handler) (uint32_t, uint32_t));
+void ksz8851_reg_setbits(uint16_t reg, uint16_t bits_to_set);
+void ksz8851_reg_clrbits(uint16_t reg, uint16_t bits_to_clr);
+void ksz8851_fifo_read(uint8_t *buf, uint32_t len);
+void ksz8851_fifo_write(uint8_t *buf, uint32_t ulActualLength, uint32_t ulFIFOLength);
+void ksz8851_fifo_dummy(uint32_t len);
+void ksz8851_reg_write(uint16_t reg, uint16_t wrdata);
+uint16_t ksz8851_reg_read(uint16_t reg);
+uint32_t ksz8851snl_init(void);
+uint32_t ksz8851snl_reinit(void);
+
+uint32_t ksz8851snl_reset_rx( void );
+uint32_t ksz8851snl_reset_tx( void );
+
+#endif /* KSZ8851SNL_H_INCLUDED */