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FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP,

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which was brought into the main download in FreeRTOS V10.0.0.  FreeRTOS+TCP can
be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches
applied to FreeRTOS+TCP.
This commit is contained in:
Richard Barry
2018-08-23 00:00:20 +00:00
parent 3a1631fda3
commit a11b1a494d
347 changed files with 23 additions and 146241 deletions
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4
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/ReadMe.txt Normal file
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FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP,
which was brought into the main download in FreeRTOS V10.0.0. FreeRTOS+TCP can
be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches
applied to FreeRTOS+TCP.

233
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.cproject
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@ -1,233 +0,0 @@
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&lt;peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40084000"/&gt;&#13;
&lt;peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40085000"/&gt;&#13;
&lt;peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x400c3000"/&gt;&#13;
&lt;peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x400c4000"/&gt;&#13;
&lt;peripheralInstance derived_from="SCU" id="SCU" location="0x40086000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x40087000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x40088000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40089000"/&gt;&#13;
&lt;peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400a0000"/&gt;&#13;
&lt;peripheralInstance derived_from="I2C0" id="I2C0" location="0x400a1000"/&gt;&#13;
&lt;peripheralInstance derived_from="I2C1" id="I2C1" location="0x400e0000"/&gt;&#13;
&lt;peripheralInstance derived_from="I2S0" id="I2S0" location="0x400a2000"/&gt;&#13;
&lt;peripheralInstance derived_from="I2S1" id="I2S1" location="0x400a3000"/&gt;&#13;
&lt;peripheralInstance derived_from="C-CAN1" id="C-CAN1" location="0x400a4000"/&gt;&#13;
&lt;peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x400c0000"/&gt;&#13;
&lt;peripheralInstance derived_from="QEI" id="QEI" location="0x400c6000"/&gt;&#13;
&lt;peripheralInstance derived_from="GIMA" id="GIMA" location="0x400c7000"/&gt;&#13;
&lt;peripheralInstance derived_from="DAC" id="DAC" location="0x400e1000"/&gt;&#13;
&lt;peripheralInstance derived_from="C-CAN0" id="C-CAN0" location="0x400e2000"/&gt;&#13;
&lt;peripheralInstance derived_from="ADC0" id="ADC0" location="0x400e3000"/&gt;&#13;
&lt;peripheralInstance derived_from="ADC1" id="ADC1" location="0x400e4000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x400f4000"/&gt;&#13;
&lt;/chip&gt;&#13;
&lt;processor&gt;&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
&lt;/processor&gt;&#13;
&lt;link href="nxp_lpc18xx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
&lt;/info&gt;&#13;
&lt;/infoList&gt;&#13;
&lt;/TargetConfig&gt;</projectStorage>
</storageModule>
<storageModule moduleId="refreshScope" versionNumber="2">
<configuration configurationName="Release">
<resource resourceType="PROJECT" workspacePath="/FreeRTOS_UDP_Demo"/>
</configuration>
<configuration configurationName="Debug">
<resource resourceType="PROJECT" workspacePath="/FreeRTOS_UDP_Demo"/>
</configuration>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.56486929;com.crt.advproject.config.exe.debug.56486929.;com.crt.advproject.gcc.exe.debug.517029683;com.crt.advproject.compiler.input.927112517">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.56486929;com.crt.advproject.config.exe.debug.56486929.;com.crt.advproject.gas.exe.debug.281614531;com.crt.advproject.assembler.input.1243504913">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="com.crt.advproject"/>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
</cproject>

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FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.project
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>FreeRTOS_UDP_Demo</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>

2
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.cdt.codan.core.prefs
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@ -1,2 +0,0 @@
eclipse.preferences.version=1
useParentScope=false

2
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.ltk.core.refactoring.prefs
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@ -1,2 +0,0 @@
eclipse.preferences.version=1
org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false

664
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CLI-commands.c
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80
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CreateProjectDirectoryStructure.bat
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REM This file should be executed from the command line prior to the first
REM build. It will be necessary to refresh the Eclipse project once the
REM .bat file has been executed (normally just press F5 to refresh).
REM Copies all the required files from their location within the standard
REM FreeRTOS directory structure to under the Eclipse project directory.
REM This permits the Eclipse project to be used in 'managed' mode and without
REM having to setup any linked resources.
REM Standard paths
SET FREERTOS_SOURCE=..\..\..\FreeRTOS\Source
SET FREERTOS_UDP_SOURCE=..\..\Source\FreeRTOS-Plus-UDP
SET FREERTOS_CLI_SOURCE=..\..\Source\FreeRTOS-Plus-CLI
set FREERTOS_TRACE_RECORDER_SOURCE=..\..\Source\FreeRTOS-Plus-Trace
REM Have the files already been copied?
IF EXIST FreeRTOS_Source Goto END
REM Create the required directory structure.
MD FreeRTOS_Source
MD FreeRTOS_Source\include
MD FreeRTOS_Source\portable\
MD FreeRTOS_Source\portable\GCC
MD FreeRTOS_Source\portable\GCC\ARM_CM3
MD FreeRTOS_Source\portable\MemMang
MD FreeRTOS_Plus_UDP
MD FreeRTOS_Plus_UDP\include
MD FreeRTOS_Plus_UDP\portable
MD FreeRTOS_Plus_UDP\portable\Compiler
MD FreeRTOS_Plus_UDP\portable\Compiler\GCC
MD FreeRTOS_Plus_UDP\portable\BufferManagement
MD FreeRTOS_Plus_UDP\portable\NetworkInterface
MD FreeRTOS_Plus_UDP\portable\NetworkInterface\LPC18xx
MD FreeRTOS_Plus_CLI
MD Examples\Ethernet
REM Copy the core kernel files into the SDK projects directory
copy %FREERTOS_SOURCE%\tasks.c FreeRTOS_Source
copy %FREERTOS_SOURCE%\queue.c FreeRTOS_Source
copy %FREERTOS_SOURCE%\list.c FreeRTOS_Source
copy %FREERTOS_SOURCE%\timers.c FreeRTOS_Source
REM Copy the common header files into the SDK projects directory
copy %FREERTOS_SOURCE%\include\*.* FreeRTOS_Source\include
REM Copy the portable layer files into the projects directory
copy %FREERTOS_SOURCE%\portable\GCC\ARM_CM3\*.* FreeRTOS_Source\portable\GCC\ARM_CM3
REM Copy the memory allocation file into the project's directory
copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c FreeRTOS_Source\portable\MemMang
REM Copy the FreeRTOS+UDP core files
copy %FREERTOS_UDP_SOURCE%\*.c FreeRTOS_Plus_UDP
copy %FREERTOS_UDP_SOURCE%\readme.txt FreeRTOS_Plus_UDP
copy %FREERTOS_UDP_SOURCE%\include\*.* FreeRTOS_Plus_UDP\include
REM Copy the FreeRTOS+UDP portable layer files
copy %FREERTOS_UDP_SOURCE%\portable\NetworkInterface\LPC18xx\Using_CMSISv2p10_LPC18xx_DriverLib\*.* FreeRTOS_Plus_UDP\portable\NetworkInterface\LPC18xx
copy %FREERTOS_UDP_SOURCE%\portable\BufferManagement\BufferAllocation_2.c FreeRTOS_Plus_UDP\portable\BufferManagement
copy %FREERTOS_UDP_SOURCE%\portable\Compiler\GCC\*.* FreeRTOS_Plus_UDP\portable\Compiler\GCC
REM Copy the FreeRTOS+CLI files
copy %FREERTOS_CLI_SOURCE%\*.* FreeRTOS_Plus_CLI
REM Copy the FreeRTOS+Trace recorder files
copy %FREERTOS_TRACE_RECORDER_SOURCE%\*.* ThirdParty\FreeRTOS_Plus_Trace_Recorder
copy %FREERTOS_TRACE_RECORDER_SOURCE%\include\*.* ThirdParty\FreeRTOS_Plus_Trace_Recorder\include
REM Copy the echo client example implementation
copy ..\Common\FreeRTOS_Plus_UDP_Demos\EchoClients\TwoEchoClients.c Examples\Ethernet
copy ..\Common\FreeRTOS_Plus_UDP_Demos\EchoClients\TwoEchoClients.h Examples\include
REM Copy the example IP trace macro implementation
copy ..\Common\FreeRTOS_Plus_UDP_Demos\TraceMacros\Example1\DemoIPTrace.c Examples\Ethernet
copy ..\Common\FreeRTOS_Plus_UDP_Demos\TraceMacros\Example1\DemoIPTrace.h Examples\include
REM Copy the CLI commands implementation into the project directory.
copy ..\Common\FreeRTOS_Plus_UDP_Demos\CLICommands\CLI-commands.c .
: END

301
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/USB_CDC/CDCCommandConsole.c
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40
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/CDCCommandConsole.h
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/*
* FreeRTOS Kernel V10.0.1
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef CDC_COMMAND_CONSOLE_H
#define CDC_COMMAND_CONSOLE_H
/*
* Create the task that implements a command console using the USB virtual com
* port driver for intput and output.
*/
void vCDCCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority );
#endif /* CDC_COMMAND_CONSOLE_H */

38
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/TwoEchoClients.h
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/*
* FreeRTOS Kernel V10.0.1
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef TWO_ECHO_CLIENTS_H
#define TWO_ECHO_CLIENTS_H
/*
* Create the two UDP echo client tasks. One task uses the standard interface
* to send to and receive from an echo server. The other task uses the zero
* copy interface to send to and receive from an echo server.
*/
void vStartEchoClientTasks( uint16_t usTaskStackSize, UBaseType_t uxTaskPriority );
#endif /* TWO_ECHO_CLIENTS_H */

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FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Flash_map.xml
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<info flash_driver='LPC1850A_4350A_SPIFI.cfx'>
<chip>
<memory id='Flash' type='Flash' is_ro='true' can_program='true'></memory>
<memory id='RAM' type='RAM'></memory>
<memoryInstance id='SPIFlash' derived_from='Flash' location='0x14000000' size='0x400000' edited='true'/>
<memoryInstance id='RamLoc96' derived_from='RAM' location='0x10000000' size='0x18000' edited='true'/>
<memoryInstance id='RamLoc40' derived_from='RAM' location='0x10080000' size='0xa000' edited='true'/>
<memoryInstance id='RamAHB32' derived_from='RAM' location='0x20000000' size='0x8000' edited='true'/>
<memoryInstance id='RamAHB16' derived_from='RAM' location='0x20008000' size='0x4000' edited='true'/>
<memoryInstance id='RamAHB_ETB16' derived_from='RAM' location='0x2000c000' size='0x4000' edited='true'/>
</chip>
</info>

242
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSConfig.h
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/*
* FreeRTOS Kernel V10.0.1
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <stdint.h>
extern uint32_t SystemCoreClock;
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
* http://www.freertos.org/a00110.html
*
* The bottom of this file contains some constants specific to running the UDP
* stack in this demo. Constants specific to FreeRTOS+UDP itself (rather than
* the demo) are contained in FreeRTOSIPConfig.h.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#define configUSE_TICKLESS_IDLE 0
#define configMAX_PRIORITIES ( 7 )
#define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configTICK_RATE_HZ 100
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 300 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40 * 1024 ) ) /* Has not effect in this demo as the heap is manually pointed to AHB RAM. */
#define configMAX_TASK_NAME_LEN ( 9 )
#define configIDLE_SHOULD_YIELD 0
#define configQUEUE_REGISTRY_SIZE 10
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configUSE_MUTEXES 1
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_ALTERNATIVE_API 0
#define configUSE_RECURSIVE_MUTEXES 1
/* Hook function related definitions. */
#define configUSE_TICK_HOOK 0
#define configUSE_IDLE_HOOK 0
#define configUSE_MALLOC_FAILED_HOOK 1
#define configCHECK_FOR_STACK_OVERFLOW 2
/* Software timer related definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
/* Run time stats gathering definitions. */
void vMainConfigureTimerForRunTimeStats( void );
uint32_t ulMainGetRunTimeCounterValue( void );
#define configGENERATE_RUN_TIME_STATS 1
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vMainConfigureTimerForRunTimeStats()
#define portGET_RUN_TIME_COUNTER_VALUE() ulMainGetRunTimeCounterValue()
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_uxTaskGetStackHighWaterMark 1
#define INCLUDE_xTimerGetTimerTaskHandle 0
#define INCLUDE_xTaskGetIdleTaskHandle 0
#define INCLUDE_xQueueGetMutexHolder 1
/* This demo makes use of one or more example stats formatting functions. These
format the raw data provided by the uxTaskGetSystemState() function in to human
readable ASCII form. See the notes in the implementation of vTaskList() within
FreeRTOS/Source/tasks.c for limitations. */
#define configUSE_STATS_FORMATTING_FUNCTIONS 1
/* Assert statement defined for debug builds. */
#ifdef DEBUG
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
#endif
/* Interrupt priority configuration settings follow.
http://www.freertos.org/RTOS-Cortex-M3-M4.html */
/* Use the system definition for the number of interrupt priorities, if there
is one */
#ifdef __NVIC_PRIO_BITS
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 3 /* 8 priority levels */
#endif
/* The maximum priority an interrupt that uses an interrupt safe FreeRTOS API
function can have. Note that lower priority have numerically higher values. */
#define configMAX_LIBRARY_INTERRUPT_PRIORITY ( 5 )
/* The minimum possible interrupt priority. */
#define configMIN_LIBRARY_INTERRUPT_PRIORITY ( 7 )
/* The lowest priority. */
#define configKERNEL_INTERRUPT_PRIORITY ( configMIN_LIBRARY_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Priority 5, or 248 as only the top five bits are implemented. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configMAX_LIBRARY_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler SysTick_Handler
/*
* DEMO APPLICATION SPECIFIC DEFINITIONS FOLLOW FROM HERE
*/
/* Set to 1 to include "trace start" and "trace stop" CLI commands. These
commands start and stop the FreeRTOS+Trace recording. */
#define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0
/* Dimensions a buffer that can be used by the FreeRTOS+CLI command
interpreter. See the FreeRTOS+CLI documentation for more information:
http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */
#define configCOMMAND_INT_MAX_OUTPUT_SIZE 1024
/* The priority used by the Ethernet MAC driver interrupt. */
#define configMAC_INTERRUPT_PRIORITY ( configMAX_LIBRARY_INTERRUPT_PRIORITY )
/* If configINCLUDE_DEMO_DEBUG_STATS is set to one, then a few basic IP trace
macros are defined to gather some UDP stack statistics that can then be viewed
through the CLI interface. See
http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Trace.shtml*/
#define configINCLUDE_DEMO_DEBUG_STATS 1
/* The LPC1830 Ethernet peripheral uses a DMA to transmit and receive packets.
The DMA uses a chain of descriptors to reference Ethernet buffers, and provide
information on the state of each buffer (full/empty/error/etc.).
configNUM_RX_ETHERNET_DMA_DESCRIPTORS defines the total number of receive
descriptors (descriptors that point to buffers into which the DMA will write
packets received from the network). An Ethernet buffer is assigned to each
descriptor. Having too few descriptors will impact reliability because the DMA
will have to drop packets that are received when there are no receive
descriptors free. It is however only necessary to have a couple of free
descriptors at a time, and having more wastes the RAM used by the Ethernet
buffers that are surplus to requirements. */
#define configNUM_RX_ETHERNET_DMA_DESCRIPTORS 4
/* The LPC1830 Ethernet peripheral uses a DMA to transmit and receive packets.
The DMA uses a chain of descriptors to reference Ethernet buffers that are
waiting to be sent onto the network. configNUM_TX_ETHERNET_DMA_DESCRIPTORS
defines the total number of transmit descriptors. An Ethernet buffer is
not assigned to a transmit descriptor until data is actually sent, but will
remain assigned to the descriptor until the descriptor is re-used. It is not
necessary to have many transmit descriptors as the IP stack task will be held
in the Blocked state (so other tasks can run) until a descriptor becomes
available if it attempts to transmit when all the descriptors are in use. See
the iptraceWAITING_FOR_TX_DMA_DESCRIPTOR() IP trace macro. */
#define configNUM_TX_ETHERNET_DMA_DESCRIPTORS 1
/* The address of an echo server that will be used by the two demo echo client
tasks.
http://FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Common_Echo_Clients.shtml */
#define configECHO_SERVER_ADDR0 172
#define configECHO_SERVER_ADDR1 25
#define configECHO_SERVER_ADDR2 218
#define configECHO_SERVER_ADDR3 103
/* MAC address configuration. In a deployed production system this would
probably be read from an EEPROM. In the demo it is just hard coded. Make sure
each node on the network has a unique MAC address. */
#define configMAC_ADDR0 0x00
#define configMAC_ADDR1 0x01
#define configMAC_ADDR2 0x02
#define configMAC_ADDR3 0x03
#define configMAC_ADDR4 0x04
#define configMAC_ADDR5 0x08
/* Default IP address configuration. Used in ipconfigUSE_DNS is set to 0, or
ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */
#define configIP_ADDR0 172
#define configIP_ADDR1 25
#define configIP_ADDR2 218
#define configIP_ADDR3 200
/* Default gateway IP address configuration. Used in ipconfigUSE_DNS is set to
0, or ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */
#define configGATEWAY_ADDR0 172
#define configGATEWAY_ADDR1 25
#define configGATEWAY_ADDR2 218
#define configGATEWAY_ADDR3 1
/* Default DNS server configuration. OpenDNS addresses are 208.67.222.222 and
208.67.220.220. Used in ipconfigUSE_DNS is set to 0, or ipconfigUSE_DNS is set
to 1 but a DNS server cannot be contacted.*/
#define configDNS_SERVER_ADDR0 208
#define configDNS_SERVER_ADDR1 67
#define configDNS_SERVER_ADDR2 222
#define configDNS_SERVER_ADDR3 222
/* Defalt netmask configuration. Used in ipconfigUSE_DNS is set to 0, or
ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */
#define configNET_MASK0 255
#define configNET_MASK1 255
#define configNET_MASK2 255
#define configNET_MASK3 0
/* Only include the trace macro definitions required by FreeRTOS+Trace if
the trace start and trace stop CLI commands are included. */
#include "trcRecorder.h"
#endif /* FREERTOS_CONFIG_H */

222
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSIPConfig.h
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@ -1,222 +0,0 @@
/*
* FreeRTOS+UDP V1.0.4
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*****************************************************************************
*
* See the following URL for configuration information.
* http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Configuration.shtml
*
*****************************************************************************/
#ifndef FREERTOS_IP_CONFIG_H
#define FREERTOS_IP_CONFIG_H
/* The IP stack executes it its own task (although any application task can make
use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY
sets the priority of the task that executes the IP stack. The priority is a
standard FreeRTOS task priority so can take any value from 0 (the lowest
priority) to (configMAX_PRIORITIES - 1) (the highest priority).
configMAX_PRIORITIES is a standard FreeRTOS configuration parameter defined in
FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to
the priority assigned to the task executing the IP stack relative to the
priority assigned to tasks that use the IP stack. */
#define ipconfigUDP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )
/* The size, in words (not bytes), of the stack allocated to the FreeRTOS+UDP
task. This setting is less important when the FreeRTOS Win32 simulator is used
as the Win32 simulator only stores a fixed amount of information on the task
stack. FreeRTOS includes optional stack overflow detection, see:
http://www.freertos.org/Stacks-and-stack-overflow-checking.html */
#define ipconfigUDP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 3 )
/* ipconfigRAND32() is called by the IP stack to generate a random number that
is then used as a DHCP transaction number. Random number generation is performed
via this macro to allow applications to use their own random number generation
method. For example, it might be possible to generate a random number by
sampling noise on an analogue input. */
#define ipconfigRAND32() 1
/* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+UDP will call the
network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK
is not set to 1 then the network event hook will never be called. See
http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/API/vApplicationIPNetworkEventHook.shtml
*/
#define ipconfigUSE_NETWORK_EVENT_HOOK 1
/* Sockets have a send block time attribute. If FreeRTOS_sendto() is called but
a network buffer cannot be obtained then the calling task is held in the Blocked
state (so other tasks can continue to executed) until either a network buffer
becomes available or the send block time expires. If the send block time expires
then the send operation is aborted. The maximum allowable send block time is
capped to the value set by ipconfigMAX_SEND_BLOCK_TIME_TICKS. Capping the
maximum allowable send block time prevents prevents a deadlock occurring when
all the network buffers are in use and the tasks that process (and subsequently
free) the network buffers are themselves blocked waiting for a network buffer.
ipconfigMAX_SEND_BLOCK_TIME_TICKS is specified in RTOS ticks. A time in
milliseconds can be converted to a time in ticks by dividing the time in
milliseconds by portTICK_RATE_MS. */
#define ipconfigMAX_SEND_BLOCK_TIME_TICKS ( 20 / portTICK_RATE_MS )
/* If ipconfigUSE_DHCP is 1 then FreeRTOS+UDP will attempt to retrieve an IP
address, netmask, DNS server address and gateway address from a DHCP server. If
ipconfigUSE_DHCP is 0 then FreeRTOS+UDP will use a static IP address. The
stack will revert to using the static IP address even when ipconfigUSE_DHCP is
set to 1 if a valid configuration cannot be obtained from a DHCP server for any
reason. The static configuration used is that passed into the stack by the
FreeRTOS_IPInit() function call. */
#define ipconfigUSE_DHCP 1
/* When ipconfigUSE_DHCP is set to 1, DHCP requests will be sent out at
increasing time intervals until either a reply is received from a DHCP server
and accepted, or the interval between transmissions reaches
ipconfigMAXIMUM_DISCOVER_TX_PERIOD. The IP stack will revert to using the
static IP address passed as a parameter to FreeRTOS_IPInit() if the
re-transmission time interval reaches ipconfigMAXIMUM_DISCOVER_TX_PERIOD without
a DHCP reply being received. */
#ifdef _WINDOWS_
/* The windows simulated time is not real time so the max delay is much
shorter. */
#define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 999 / portTICK_RATE_MS )
#else
#define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 120000 / portTICK_RATE_MS )
#endif /* _WINDOWS_ */
/* The ARP cache is a table that maps IP addresses to MAC addresses. The IP
stack can only send a UDP message to a remove IP address if it knowns the MAC
address associated with the IP address, or the MAC address of the router used to
contact the remote IP address. When a UDP message is received from a remote IP
address the MAC address and IP address are added to the ARP cache. When a UDP
message is sent to a remote IP address that does not already appear in the ARP
cache then the UDP message is replaced by a ARP message that solicits the
required MAC address information. ipconfigARP_CACHE_ENTRIES defines the maximum
number of entries that can exist in the ARP table at any one time. */
#define ipconfigARP_CACHE_ENTRIES 6
/* ARP requests that do not result in an ARP response will be re-transmitted a
maximum of ipconfigMAX_ARP_RETRANSMISSIONS times before the ARP request is
aborted. */
#define ipconfigMAX_ARP_RETRANSMISSIONS ( 5 )
/* ipconfigMAX_ARP_AGE defines the maximum time between an entry in the ARP
table being created or refreshed and the entry being removed because it is stale.
New ARP requests are sent for ARP cache entries that are nearing their maximum
age. ipconfigMAX_ARP_AGE is specified in tens of seconds, so a value of 150 is
equal to 1500 seconds (or 25 minutes). */
#define ipconfigMAX_ARP_AGE 150
/* Implementing FreeRTOS_inet_addr() necessitates the use of string handling
routines, which are relatively large. To save code space the full
FreeRTOS_inet_addr() implementation is made optional, and a smaller and faster
alternative called FreeRTOS_inet_addr_quick() is provided. FreeRTOS_inet_addr()
takes an IP in decimal dot format (for example, "192.168.0.1") as its parameter.
FreeRTOS_inet_addr_quick() takes an IP address as four separate numerical octets
(for example, 192, 168, 0, 1) as its parameters. If
ipconfigINCLUDE_FULL_INET_ADDR is set to 1 then both FreeRTOS_inet_addr() and
FreeRTOS_indet_addr_quick() are available. If ipconfigINCLUDE_FULL_INET_ADDR is
not set to 1 then only FreeRTOS_indet_addr_quick() is available. */
#define ipconfigINCLUDE_FULL_INET_ADDR 1
/* ipconfigNUM_NETWORK_BUFFERS defines the total number of network buffer that
are available to the IP stack. The total number of network buffers is limited
to ensure the total amount of RAM that can be consumed by the IP stack is capped
to a pre-determinable value. */
#define ipconfigNUM_NETWORK_BUFFERS 10
/* A FreeRTOS queue is used to send events from application tasks to the IP
stack. ipconfigEVENT_QUEUE_LENGTH sets the maximum number of events that can
be queued for processing at any one time. The event queue must be a minimum of
5 greater than the total number of network buffers. */
#define ipconfigEVENT_QUEUE_LENGTH ( ipconfigNUM_NETWORK_BUFFERS + 5 )
/* The address of a socket is the combination of its IP address and its port
number. FreeRTOS_bind() is used to manually allocate a port number to a socket
(to 'bind' the socket to a port), but manual binding is not normally necessary
for client sockets (those sockets that initiate outgoing connections rather than
wait for incoming connections on a known port number). If
ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 1 then calling
FreeRTOS_sendto() on a socket that has not yet been bound will result in the IP
stack automatically binding the socket to a port number from the range
socketAUTO_PORT_ALLOCATION_START_NUMBER to 0xffff. If
ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 0 then calling FreeRTOS_sendto()
on a socket that has not yet been bound will result in the send operation being
aborted. */
#define ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND 1
/* Defines the Time To Live (TTL) values used in outgoing UDP packets. */
#define updconfigIP_TIME_TO_LIVE 128
/* If ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is set to 1 then UDP packets that
contain more data than will fit in a single network frame will be fragmented
across multiple IP packets. Also see the ipconfigNETWORK_MTU setting. If
ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must
be divisible by 8. Setting ipconfigCAN_FRAGMENT_OUTGOING_PACKETS to 1 will
increase both the code size and execution time. */
#define ipconfigCAN_FRAGMENT_OUTGOING_PACKETS 0
/* The MTU is the maximum number of bytes the payload of a network frame can
contain. For normal Ethernet V2 frames the maximum MTU is 1500. Setting a
lower value can save RAM, depending on the buffer management scheme used. If
ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must
be divisible by 8. */
#define ipconfigNETWORK_MTU 586
/* Set ipconfigUSE_DNS to 1 to include a basic DNS client/resolver. DNS is used
through the FreeRTOS_gethostbyname() API function. */
#define ipconfigUSE_DNS 1
/* If ipconfigREPLY_TO_INCOMING_PINGS is set to 1 then the IP stack will
generate replies to incoming ICMP echo (ping) requests. */
#define ipconfigREPLY_TO_INCOMING_PINGS 1
/* If ipconfigSUPPORT_OUTGOING_PINGS is set to 1 then the
FreeRTOS_SendPingRequest() API function is available. */
#define ipconfigSUPPORT_OUTGOING_PINGS 1
/* Used for stack testing only, and must be implemented in the network
interface. */
#define updconfigLOOPBACK_ETHERNET_PACKETS 0
/* If ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES is set to 1 then Ethernet frames
that are not in Ethernet II format will be dropped. This option is included for
potential future IP stack developments. */
#define ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES 1
/* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1 then it is the
responsibility of the Ethernet interface to filter out packets that are of no
interest. If the Ethernet interface does not implement this functionality, then
set ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES to 0 to have the IP stack
perform the filtering instead (it is much less efficient for the stack to do it
because the packet will already have been passed into the stack). If the
Ethernet driver does all the necessary filtering in hardware then software
filtering can be removed by using a value other than 1 or 0. */
#define ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES 2
/* The example IP trace macros are included here so the definitions are
available in all the FreeRTOS+UDP source files. */
#include "DemoIPTrace.h"
#endif /* FREERTOS_IP_CONFIG_H */

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/*
* FreeRTOS Kernel V10.0.1
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Simple LED IO functions. LED 0 is toggled by a timer every half second. */
/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "timers.h"
/* Library includes. */
#include "lpc18xx_gpio.h"
#include "lpc18xx_scu.h"
#include "lpc18xx_cgu.h"
#define ledTOGGLE_RATE ( 500 / portTICK_RATE_MS )
#define ledLED0_PORT 1
#define ledLED0_BIT ( 1UL << 11UL )
#define ledLED1_PORT 2
#define ledLED1_BIT ( 1UL << 12UL )
/*
* Toggles an LED just to show the application is running.
*/
static void prvLEDToggleTimerCallback( xTimerHandle xTimer );
/*-----------------------------------------------------------*/
void vLEDsInitialise( void )
{
static xTimerHandle xLEDToggleTimer = NULL;
/* Set the LED pin-muxing and configure as output. */
scu_pinmux( 0x2 , 11, MD_PUP, FUNC0 );
scu_pinmux( 0x2 , 12, MD_PUP, FUNC0 );
GPIO_SetDir( ledLED0_PORT, ledLED0_BIT, 1 );
GPIO_SetDir( ledLED1_PORT, ledLED1_BIT, 1 );
/* Create the timer used to toggle LED0. */
xLEDToggleTimer = xTimerCreate( "LEDTmr", /* Just a text name to associate with the timer, useful for debugging, but not used by the kernel. */
ledTOGGLE_RATE, /* The period of the timer. */
pdTRUE, /* This timer will autoreload, so uxAutoReload is set to pdTRUE. */
NULL, /* The timer ID is not used, so can be set to NULL. */
prvLEDToggleTimerCallback ); /* The callback function executed each time the timer expires. */
/* Sanity check that the timer was actually created. */
configASSERT( xLEDToggleTimer );
/* Start the timer. If this is called before the scheduler is started then
the block time will automatically get changed to 0 (from portMAX_DELAY). */
xTimerStart( xLEDToggleTimer, portMAX_DELAY );
}
/*-----------------------------------------------------------*/
static void prvLEDToggleTimerCallback( xTimerHandle xTimer )
{
static uint8_t ucState = 0;
/* Remove compiler warnings. */
( void ) xTimer;
/* Just toggle an LED to show the program is running. */
if( ucState == 0 )
{
GPIO_SetValue( ledLED0_PORT, ledLED0_BIT );
}
else
{
GPIO_ClearValue( ledLED0_PORT, ledLED0_BIT );
}
ucState = !ucState;
}

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This demo is documented on the following web page:
http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/RTOS_UDP_and_CLI_LPC1830_NGX.shtml
The FreeRTOS+UDP API is documented on the following web page:
http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/FreeRTOS_UDP_API_Functions.shtml
Other information, including a FreeRTOS+UDP primer, a description of the
directory structure, and a glossary of networking terminology, can be found in
the FreeRTOS+UDP portal:
http://www.FreeRTOS.org/udp

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FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP,
which was brought into the main download in FreeRTOS V10.0.0. FreeRTOS+TCP can
be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches
applied to FreeRTOS+TCP.

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/*
* FreeRTOS Kernel V10.0.1
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* FreeRTOS includes. */
#include "FreeRTOS.h"
/* Utility functions to implement run time stats on Cortex-M CPUs. The collected
run time data can be viewed through the CLI interface. See the following URL for
more information on run time stats:
http://www.freertos.org/rtos-run-time-stats.html */
/* Addresses of registers in the Cortex-M debug hardware. */
#define rtsDWT_CYCCNT ( *( ( unsigned long * ) 0xE0001004 ) )
#define rtsDWT_CONTROL ( *( ( unsigned long * ) 0xE0001000 ) )
#define rtsSCB_DEMCR ( *( ( unsigned long * ) 0xE000EDFC ) )
#define rtsTRCENA_BIT ( 0x01000000UL )
#define rtsCOUNTER_ENABLE_BIT ( 0x01UL )
/* Simple shift divide for scaling to avoid an overflow occurring too soon. The
number of bits to shift depends on the clock speed. */
#define runtimeSLOWER_CLOCK_SPEEDS ( 70000000UL )
#define runtimeSHIFT_13 13
#define runtimeOVERFLOW_BIT_13 ( 1UL << ( 32UL - runtimeSHIFT_13 ) )
#define runtimeSHIFT_14 14
#define runtimeOVERFLOW_BIT_14 ( 1UL << ( 32UL - runtimeSHIFT_14 ) )
/*-----------------------------------------------------------*/
void vMainConfigureTimerForRunTimeStats( void )
{
/* Enable TRCENA. */
rtsSCB_DEMCR = rtsSCB_DEMCR | rtsTRCENA_BIT;
/* Reset counter. */
rtsDWT_CYCCNT = 0;
/* Enable counter. */
rtsDWT_CONTROL = rtsDWT_CONTROL | rtsCOUNTER_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
uint32_t ulMainGetRunTimeCounterValue( void )
{
static unsigned long ulLastCounterValue = 0UL, ulOverflows = 0;
unsigned long ulValueNow;
ulValueNow = rtsDWT_CYCCNT;
/* Has the value overflowed since it was last read. */
if( ulValueNow < ulLastCounterValue )
{
ulOverflows++;
}
ulLastCounterValue = ulValueNow;
/* Cannot use configCPU_CLOCK_HZ directly as it may itself not be a constant
but instead map to a variable that holds the clock speed. */
/* There is no prescale on the counter, so simulate in software. */
if( configCPU_CLOCK_HZ < runtimeSLOWER_CLOCK_SPEEDS )
{
ulValueNow >>= runtimeSHIFT_13;
ulValueNow += ( runtimeOVERFLOW_BIT_13 * ulOverflows );
}
else
{
ulValueNow >>= runtimeSHIFT_14;
ulValueNow += ( runtimeOVERFLOW_BIT_14 * ulOverflows );
}
return ulValueNow;
}
/*-----------------------------------------------------------*/

BIN
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/CMSIS END USER LICENCE AGREEMENT.pdf vendored
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CMSIS : Cortex Microcontroller Software Interface Standard
==========================================================
Introduction
~~~~~~~~~~~~
CMSIS defines for a Cortex-M Microcontroller System:
* A common way to access peripheral registers and a
common way to define exception vectors.
* The register names of the Core Peripherals and the
names of the Core Exception Vectors.
* An device independent interface for RTOS Kernels
including a debug channel.
By using CMSIS compliant software components, the user can
easier re-use template code. CMSIS is intended to enable the
combination of software components from multiple middleware
vendors.
This project contains appropriate files for this MCU family
taken from CMSIS. A full copy of the CMSIS files, together
with additional information on CMSIS can be found at:
http://www.onarm.com/
http://www.arm.com/
Documentation
~~~~~~~~~~~~~
The standard CMSIS documentation can be found within the
Code Red IDE help system, via:
Help -> Help Contents -> Code Red Product Documentation -> CMSIS
More information on the use of CMSIS within the Code Red IDE
can be found in the Support area of the Code Red website at
http://www.code-red-tech.com/
At the time of writing, the CMSIS FAQ can be found directly
at:
http://support.code-red-tech.com/CodeRedWiki/Support4CMSIS

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FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/LPC1800CMSIS_ReleaseNotes.txt vendored
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NXP's documentation for their peripheral driver library can be found
as a Microsoft Compiled HTML Help file (.chm) within the LPC18xx
CMSIS Standard Peripheral Driver Library download on NXP's website.
At the time of writing, this can be found at the following link:
http://lpcware.com/file_filter/nxp?term_node_tid_depth=All&term_node_tid_depth_1=103

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/**********************************************************************
* $Id$ debug_frmwrk.h 2011-06-02
*//**
* @file debug_frmwrk.h
* @brief Contains some utilities that used for debugging through UART
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup DEBUG_FRMWRK DEBUG FRAMEWORK
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef DEBUG_FRMWRK_H_
#define DEBUG_FRMWRK_H_
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_uart.h"
#define VCOM_DEBUG_MESSEGES
//#define UART_DEBUG_MESSEGES
#define USED_UART_DEBUG_PORT 1
#if (USED_UART_DEBUG_PORT==0)
#define DEBUG_UART_PORT LPC_UART0
#elif (USED_UART_DEBUG_PORT==1)
#define DEBUG_UART_PORT LPC_UART1
#endif
#define _DBG(x) _db_msg((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBG_(x) _db_msg_((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBC(x) _db_char((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBD(x) _db_dec((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBD16(x) _db_dec_16((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBD32(x) _db_dec_32((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBH(x) _db_hex((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBH16(x) _db_hex_16((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBH32(x) _db_hex_32((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DG _db_get_char((LPC_USARTn_Type*)DEBUG_UART_PORT)
void lpc_printf (const char *format, ...);
extern void (*_db_msg)(LPC_USARTn_Type *UARTx, const void *s);
extern void (*_db_msg_)(LPC_USARTn_Type *UARTx, const void *s);
extern void (*_db_char)(LPC_USARTn_Type *UARTx, uint8_t ch);
extern void (*_db_dec)(LPC_USARTn_Type *UARTx, uint8_t decn);
extern void (*_db_dec_16)(LPC_USARTn_Type *UARTx, uint16_t decn);
extern void (*_db_dec_32)(LPC_USARTn_Type *UARTx, uint32_t decn);
extern void (*_db_hex)(LPC_USARTn_Type *UARTx, uint8_t hexn);
extern void (*_db_hex_16)(LPC_USARTn_Type *UARTx, uint16_t hexn);
extern void (*_db_hex_32)(LPC_USARTn_Type *UARTx, uint32_t hexn);
extern uint8_t (*_db_get_char)(LPC_USARTn_Type *UARTx);
void UARTPutChar (LPC_USARTn_Type *UARTx, uint8_t ch);
void UARTPuts(LPC_USARTn_Type *UARTx, const void *str);
void UARTPuts_(LPC_USARTn_Type *UARTx, const void *str);
void UARTPutDec(LPC_USARTn_Type *UARTx, uint8_t decnum);
void UARTPutDec16(LPC_USARTn_Type *UARTx, uint16_t decnum);
void UARTPutDec32(LPC_USARTn_Type *UARTx, uint32_t decnum);
void UARTPutHex (LPC_USARTn_Type *UARTx, uint8_t hexnum);
void UARTPutHex16 (LPC_USARTn_Type *UARTx, uint16_t hexnum);
void UARTPutHex32 (LPC_USARTn_Type *UARTx, uint32_t hexnum);
uint8_t UARTGetChar (LPC_USARTn_Type *UARTx);
void debug_frmwrk_init(void);
#endif /* DEBUG_FRMWRK_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc18xx_adc.h 2011-06-02
*//**
* @file lpc18xx_adc.h
* @brief Contains all macro definitions and function prototypes
* support for ADC firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup ADC ADC (Analog to Digital Converter)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_ADC_H_
#define LPC18XX_ADC_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private macros ------------------------------------------------------------- */
/** @defgroup ADC_Private_Macros ADC Private Macros
* @{
*/
/* -------------------------- BIT DEFINITIONS ----------------------------------- */
/*********************************************************************//**
* Macro defines for ADC control register
**********************************************************************/
/** Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
#define ADC_CR_CH_SEL(n) ((1UL << n))
/** The APB clock (PCLK) is divided by (this value plus one)
* to produce the clock for the A/D */
#define ADC_CR_CLKDIV(n) ((n<<8))
/** Repeated conversions A/D enable bit */
#define ADC_CR_BURST ((1UL<<16))
/** number of accuracy bits */
#define ADC_CR_BITACC(n) (((n)<<17))
/** ADC convert in power down mode */
#define ADC_CR_PDN ((1UL<<21))
/** Start mask bits */
#define ADC_CR_START_MASK ((7UL<<24))
/** Select Start Mode */
#define ADC_CR_START_MODE_SEL(SEL) ((SEL<<24))
/** Start conversion now */
#define ADC_CR_START_NOW ((1UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
#define ADC_CR_START_CTOUT15 ((2UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
#define ADC_CR_START_CTOUT8 ((3UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
#define ADC_CR_START_ADCTRIG0 ((4UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
#define ADC_CR_START_ADCTRIG1 ((5UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
#define ADC_CR_START_MCOA2 ((6UL<<24))
/** Start conversion on a falling edge on the selected CAP/MAT signal */
#define ADC_CR_EDGE ((1UL<<27))
/*********************************************************************//**
* Macro defines for ADC Global Data register
**********************************************************************/
/** When DONE is 1, this field contains result value of ADC conversion */
#define ADC_GDR_RESULT(n) (((n>>4)&0xFFF))
/** These bits contain the channel from which the LS bits were converted */
#define ADC_GDR_CH(n) (((n>>24)&0x7))
/** This bit is 1 in burst mode if the results of one or
* more conversions was (were) lost */
#define ADC_GDR_OVERRUN_FLAG ((1UL<<30))
/** This bit is set to 1 when an A/D conversion completes */
#define ADC_GDR_DONE_FLAG ((1UL<<31))
/** This bits is used to mask for Channel */
#define ADC_GDR_CH_MASK ((7UL<<24))
/*********************************************************************//**
* Macro defines for ADC Interrupt register
**********************************************************************/
/** These bits allow control over which A/D channels generate
* interrupts for conversion completion */
#define ADC_INTEN_CH(n) ((1UL<<n))
/** When 1, enables the global DONE flag in ADDR to generate an interrupt */
#define ADC_INTEN_GLOBAL ((1UL<<8))
/*********************************************************************//**
* Macro defines for ADC Data register
**********************************************************************/
/** When DONE is 1, this field contains result value of ADC conversion */
#define ADC_DR_RESULT(n) (((n>>6)&0x3FF))
/** These bits mirror the OVERRRUN status flags that appear in the
* result register for each A/D channel */
#define ADC_DR_OVERRUN_FLAG ((1UL<<30))
/** This bit is set to 1 when an A/D conversion completes. It is cleared
* when this register is read */
#define ADC_DR_DONE_FLAG ((1UL<<31))
/*********************************************************************//**
* Macro defines for ADC Status register
**********************************************************************/
/** These bits mirror the DONE status flags that appear in the result
* register for each A/D channel */
#define ADC_STAT_CH_DONE_FLAG(n) ((n&0xFF))
/** These bits mirror the OVERRRUN status flags that appear in the
* result register for each A/D channel */
#define ADC_STAT_CH_OVERRUN_FLAG(n) (((n>>8)&0xFF))
/** This bit is the A/D interrupt flag */
#define ADC_STAT_INT_FLAG ((1UL<<16))
/*********************************************************************//**
* Macro defines for ADC Trim register
**********************************************************************/
/** Offset trim bits for ADC operation */
#define ADC_ADCOFFS(n) (((n&0xF)<<4))
/** Written to boot code*/
#define ADC_TRIM(n) (((n&0xF)<<8))
/* ------------------- CHECK PARAM DEFINITIONS ------------------------- */
/** Check ADC parameter */
#define PARAM_ADCx(n) (((uint32_t *)n)==((uint32_t *)LPC_ADC0) || ((uint32_t *)n)==((uint32_t *)LPC_ADC1))
/** Check ADC state parameter */
#define PARAM_ADC_START_ON_EDGE_OPT(OPT) ((OPT == ADC_START_ON_RISING)||(OPT == ADC_START_ON_FALLING))
/** Check ADC state parameter */
#define PARAM_ADC_DATA_STATUS(OPT) ((OPT== ADC_DATA_BURST)||(OPT== ADC_DATA_DONE))
/** Check ADC rate parameter */
#define PARAM_ADC_RATE(rate) ((rate>0)&&(rate<=200000))
/** Check ADC bits accuracy parameter */
#define PARAM_ADC_BITSACC(x) ((x>=3)&&(x<=10))
/** Check ADC channel selection parameter */
#define PARAM_ADC_CHANNEL_SELECTION(SEL) ((SEL == ADC_CHANNEL_0)||(ADC_CHANNEL_1)\
||(SEL == ADC_CHANNEL_2)|(ADC_CHANNEL_3)\
||(SEL == ADC_CHANNEL_4)||(ADC_CHANNEL_5)\
||(SEL == ADC_CHANNEL_6)||(ADC_CHANNEL_7))
/** Check ADC start option parameter */
#define PARAM_ADC_START_OPT(OPT) ((OPT == ADC_START_CONTINUOUS)||(OPT == ADC_START_NOW)\
||(OPT == ADC_START_ON_CTOUT15)||(OPT == ADC_START_ON_CTOUT8)\
||(OPT == ADC_START_ON_ADCTRIG0)||(OPT == ADC_START_ON_ADCTRIG1)\
||(OPT == ADC_START_ON_MCOA2))
/** Check ADC interrupt type parameter */
#define PARAM_ADC_TYPE_INT_OPT(OPT) ((OPT == ADC_ADINTEN0)||(OPT == ADC_ADINTEN1)\
||(OPT == ADC_ADINTEN2)||(OPT == ADC_ADINTEN3)\
||(OPT == ADC_ADINTEN4)||(OPT == ADC_ADINTEN5)\
||(OPT == ADC_ADINTEN6)||(OPT == ADC_ADINTEN7)\
||(OPT == ADC_ADGINTEN))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup ADC_Public_Types ADC Public Types
* @{
*/
/*********************************************************************//**
* @brief ADC enumeration
**********************************************************************/
/** @brief Channel Selection */
typedef enum
{
ADC_CHANNEL_0 = 0, /*!< Channel 0 */
ADC_CHANNEL_1, /*!< Channel 1 */
ADC_CHANNEL_2, /*!< Channel 2 */
ADC_CHANNEL_3, /*!< Channel 3 */
ADC_CHANNEL_4, /*!< Channel 4 */
ADC_CHANNEL_5, /*!< Channel 5 */
ADC_CHANNEL_6, /*!< Channel 6 */
ADC_CHANNEL_7 /*!< Channel 7 */
}ADC_CHANNEL_SELECTION;
/** @brief Type of start option */
typedef enum
{
ADC_START_CONTINUOUS =0, /*!< Continuous mode */
ADC_START_NOW, /*!< Start conversion now */
ADC_START_ON_CTOUT15, /*!< Start conversion when the edge selected
* by bit 27 occurs on CTOUT_15 */
ADC_START_ON_CTOUT8, /*!< Start conversion when the edge selected
* by bit 27 occurs on CTOUT_8 */
ADC_START_ON_ADCTRIG0, /*!< Start conversion when the edge selected
* by bit 27 occurs on ADCTRIG0 */
ADC_START_ON_ADCTRIG1, /*!< Start conversion when the edge selected
* by bit 27 occurs on ADCTRIG1 */
ADC_START_ON_MCOA2 /*!< Start conversion when the edge selected
* by bit 27 occurs on Motocon PWM output MCOA2 */
} ADC_START_OPT;
/** @brief Type of edge when start conversion on the selected CAP/MAT signal */
typedef enum
{
ADC_START_ON_RISING = 0, /*!< Start conversion on a rising edge
*on the selected CAP/MAT signal */
ADC_START_ON_FALLING /*!< Start conversion on a falling edge
*on the selected CAP/MAT signal */
} ADC_START_ON_EDGE_OPT;
/** @brief* ADC type interrupt enum */
typedef enum
{
ADC_ADINTEN0 = 0, /*!< Interrupt channel 0 */
ADC_ADINTEN1, /*!< Interrupt channel 1 */
ADC_ADINTEN2, /*!< Interrupt channel 2 */
ADC_ADINTEN3, /*!< Interrupt channel 3 */
ADC_ADINTEN4, /*!< Interrupt channel 4 */
ADC_ADINTEN5, /*!< Interrupt channel 5 */
ADC_ADINTEN6, /*!< Interrupt channel 6 */
ADC_ADINTEN7, /*!< Interrupt channel 7 */
ADC_ADGINTEN /*!< Individual channel/global flag done generate an interrupt */
}ADC_TYPE_INT_OPT;
/** @brief ADC Data status */
typedef enum
{
ADC_DATA_BURST = 0, /*Burst bit*/
ADC_DATA_DONE /*Done bit*/
}ADC_DATA_STATUS;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup ADC_Public_Functions ADC Public Functions
* @{
*/
/* Init/DeInit ADC peripheral ----------------*/
void ADC_Init(LPC_ADCn_Type *ADCx, uint32_t rate, uint8_t bits_accuracy);
void ADC_DeInit(LPC_ADCn_Type *ADCx);
/* Enable/Disable ADC functions --------------*/
void ADC_BurstCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState);
void ADC_PowerdownCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState);
void ADC_StartCmd(LPC_ADCn_Type *ADCx, uint8_t start_mode);
void ADC_ChannelCmd (LPC_ADCn_Type *ADCx, uint8_t Channel, FunctionalState NewState);
/* Configure ADC functions -------------------*/
void ADC_EdgeStartConfig(LPC_ADCn_Type *ADCx, uint8_t EdgeOption);
void ADC_IntConfig (LPC_ADCn_Type *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState);
/* Get ADC information functions -------------------*/
uint16_t ADC_ChannelGetData(LPC_ADCn_Type *ADCx, uint8_t channel);
FlagStatus ADC_ChannelGetStatus(LPC_ADCn_Type *ADCx, uint8_t channel, uint32_t StatusType);
uint32_t ADC_GlobalGetData(LPC_ADCn_Type *ADCx);
FlagStatus ADC_GlobalGetStatus(LPC_ADCn_Type *ADCx, uint32_t StatusType);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_ADC_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc18xx_atimer.h 2011-06-02
*//**
* @file lpc18xx_atimer.h
* @brief Contains all functions support for Alarm Timer firmware
* library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup ATIMER ATIMER (Alarm Timer)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC18XX_ATIMER_H_
#define __LPC18XX_ATIMER_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup ATIMER_Private_Macros ALARM Timer Private Macros
* @{
*/
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/** Macro to determine if it is valid ALARM TIMER peripheral */
#define PARAM_ATIMERx(n) (((uint32_t *)n)==((uint32_t *)LPC_ATIMER))
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup ATIMER_Public_Functions ATIMER Public Functions
* @{
*/
/* Init/DeInit ATIMER functions -----------*/
void ATIMER_Init(LPC_ATIMER_Type *ATIMERx, uint32_t PresetValue);
void ATIMER_DeInit(LPC_ATIMER_Type *ATIMERx);
/* ATIMER interrupt functions -------------*/
void ATIMER_IntEnable(LPC_ATIMER_Type *ATIMERx);
void ATIMER_IntDisable(LPC_ATIMER_Type *ATIMERx);
void ATIMER_ClearIntStatus(LPC_ATIMER_Type *ATIMERx);
void ATIMER_SetIntStatus(LPC_ATIMER_Type *ATIMERx);
/* ATIMER configuration functions --------*/
void ATIMER_UpdatePresetValue(LPC_ATIMER_Type *ATIMERx,uint32_t PresetValue);
uint32_t ATIMER_GetPresetValue(LPC_ATIMER_Type *ATIMERx);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC18XX_ATIMER_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc18xx_can.h 2011-06-02
*//**
* @file lpc18xx_can.h
* @brief Contains all macro definitions and function prototypes
* support for CAN firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup C_CAN C_CAN (Controller Area Network)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC18XX_CAN_H
#define __LPC18XX_CAN_H
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup C_CAN_Public_Macros C_CAN Public Macros
* @{
*/
/** In BASIC_MODE IF1 registers are used directly as TX buffer, IF2 registers are used as RX buffer.
* If not BASIC_MODE use message objects and IF registers to communicate with message buffers
*/
#define BASIC_MODE 0
/** In Silent Mode, the CAN controller is able to receive valid data frames and valid remote
* frames, but it sends only recessive bits on the CAN bus, and it cannot start a transmission
*/
#define SILENT_MODE 0
/** In Loop-back Mode, the CAN Core treats its own transmitted messages as received messages
* and stores them (if they pass acceptance filtering) into a Receive Buffer.
*/
#define LOOPBACK_MODE 0
/** Enables receiving remote frame requests */
#define REMOTE_ENABLE 1
/**
* @}
*/
/* Private Macros -------------------------------------------------------------- */
/** @defgroup C_CAN_Private_Macros C_CAN Private Macros
* @{
*/
/** MAX CAN message obj */
#define CAN_MSG_OBJ_MAX 0x0020
/** MAX data length */
#define CAN_DLC_MAX 8
/********************************************************************//**
* BRP+1 = Fpclk/(CANBitRate * QUANTAValue)
* QUANTAValue = 1 + (Tseg1+1) + (Tseg2+1)
* QUANTA value varies based on the Fpclk and sample point
* e.g. (1) sample point is 87.5%, Fpclk is 48Mhz
* the QUANTA should be 16
* (2) sample point is 90%, Fpclk is 12.5Mhz
* the QUANTA should be 10
* Fpclk = Fclk /APBDIV
* or
* BitRate = Fcclk/(APBDIV * (BRP+1) * ((Tseg1+1)+(Tseg2+1)+1))
*/
/*********************************************************************//**
* @brief CAN Bit Timing Values definitions at 8Mhz
**********************************************************************/
/** Bitrate: 100K */
#define CAN_BITRATE100K12MHZ 0x00004509
/** Bitrate: 125K */
#define CAN_BITRATE125K12MHZ 0x00004507
/** Bitrate: 250K */
#define CAN_BITRATE250K12MHZ 0x00004503
/** Bitrate: 500K */
#define CAN_BITRATE500K12MHZ 0x00004501
/** Bitrate: 1000K */
#define CAN_BITRATE1000K12MHZ 0x00004500
/*********************************************************************//**
* @brief CAN Bit Timing Values definitions at 16Mhz
**********************************************************************/
/** Bitrate: 100K */
#define CAN_BITRATE100K16MHZ 0x00005809
/** Bitrate: 125K */
#define CAN_BITRATE125K16MHZ 0x00005807
/** Bitrate: 250K */
#define CAN_BITRATE250K16MHZ 0x00005803
/** Bitrate: 500K */
#define CAN_BITRATE500K16MHZ 0x00005801
/*********************************************************************//**
* @brief CAN Bit Timing Values definitions at 24Mhz
**********************************************************************/
/** Bitrate: 100K */
#define CAN_BITRATE100K24MHZ 0x00007E09
/** Bitrate: 125K */
#define CAN_BITRATE125K24MHZ 0x0000450F
/** Bitrate: 250K */
#define CAN_BITRATE250K24MHZ 0x00004507
/** Bitrate: 500K */
#define CAN_BITRATE500K24MHZ 0x00004503
/** Bitrate: 1000K */
#define CAN_BITRATE1000K24MHZ 0x00004501
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup CAN_Public_Types CAN Public Types
* @{
*/
/*********************************************************************//**
* @brief CAN enumeration
**********************************************************************/
/**
* @brief CAN interface register type definition
*/
typedef enum CCAN_IFREG
{
CMDREQ = 0, /**< Command request */
CMDMSK = 1, /**< Command mask */
MSK1 = 2, /**< Mask 1 */
MSK2 = 3, /**< Mask 2 */
ARB1 = 4, /**< Arbitration 1 */
ARB2 = 5, /**< Arbitration 2 */
MCTRL = 6, /**< Message control */
DA1 = 7, /**< Data A1 */
DA2 = 8, /**< Data A2 */
DB1 = 9, /**< Data B1 */
DB2 = 10 /**< Data B2 */
}CCAN_IFREG_Type;
/**
* @brief CAN Clock division rate type definition
*/
typedef enum CCAN_CLKDIV
{
CLKDIV1 = 0,
CLKDIV2 = 1,
CLKDIV3 = 2,
CLKDIV5 = 3,
CLKDIV9 = 4,
CLKDIV17 = 5,
CLKDIV33 = 6,
CLKDIV65 = 7
}CCAN_CLKDIV_Type;
/********************************************************************//**
* @brief Data structure definition for a CAN message
**********************************************************************/
/**
* @brief CAN message object structure
*/
typedef struct
{
uint32_t id; /**< ID of message, if bit 30 is set then this is extended frame */
uint32_t dlc; /**< Message data length */
uint8_t data[8]; /**< Message data */
} message_object;
/**
* @brief CAN call-back function
*/
typedef void (*MSG_CB)(uint32_t msg_no);
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup CAN_Public_Functions CAN Public Functions
* @{
*/
void CAN_IRQHandler (void);
void CAN_Init( uint32_t BitClk, CCAN_CLKDIV_Type ClkDiv , MSG_CB Tx_cb, MSG_CB Rx_cb);
void CAN_ConfigureRxMessageObjects( void );
void CAN_RxInt_MessageProcess( uint8_t MsgObjNo );
void CAN_TxInt_MessageProcess( uint8_t MsgObjNo );
void CAN_Send(uint8_t msg_no, uint32_t *msg_ptr );
void CAN_Recv(uint8_t msg_no, uint32_t *msg_ptr, Bool RemoteEnable);
void CAN_ReadMsg(uint32_t msg_no, message_object* buff);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC18XX_CAN_H */
/**
* @}
*/
/*****************************************************************************
** End Of File
******************************************************************************/

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/**********************************************************************
* $Id$ lpc18xx_cgu.h 2011-06-02
*//**
* @file llpc18xx_cgu.h
* @brief Contains all macro definitions and function prototypes
* support for Clock Generation and Clock Control firmware
* library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup CGU CGU (Clock Generation Unit)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_CGU_H_
#define LPC18XX_CGU_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros -------------------------------------------------------------- */
/** @defgroup CGU_Private_Macros CGU Private Macros
* @{
*/
/** Branch clocks from CGU_BASE_SAFE */
#define CGU_ENTITY_NONE CGU_ENTITY_NUM
/** Check bit at specific position is clear or not */
#define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))
/** Check bit at specific position is set or not */
#define ISBITSET(x,bit) (x&(1<<bit))
/** Set mask */
#define ISMASKSET(x,mask) (x&mask)
/** CGU number of clock source */
#define CGU_CLKSRC_NUM (CGU_CLKSRC_IDIVE+1)
/*********************************************************************//**
* Macro defines for CGU control mask bit definitions
**********************************************************************/
/** CGU control enable mask bit */
#define CGU_CTRL_EN_MASK 1
/** CGU control clock-source mask bit */
#define CGU_CTRL_SRC_MASK (0xF<<24)
/** CGU control auto block mask bit */
#define CGU_CTRL_AUTOBLOCK_MASK (1<<11)
/*********************************************************************//**
* Macro defines for CGU PLL1 mask bit definitions
**********************************************************************/
/** CGU PLL1 feedback select mask bit */
#define CGU_PLL1_FBSEL_MASK (1<<6)
/** CGU PLL1 Input clock bypass control mask bit */
#define CGU_PLL1_BYPASS_MASK (1<<1)
/** CGU PLL1 direct CCO output mask bit */
#define CGU_PLL1_DIRECT_MASK (1<<7)
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup CGU_Public_Types CGU Public Types
* @{
*/
/*********************************************************************//**
* @brief CGU enumeration
**********************************************************************/
/*
* @brief CGU clock source enumerate definition
*/
typedef enum {
/* Clock Source */
CGU_CLKSRC_32KHZ_OSC = 0, /**< 32KHz oscillator clock source */
CGU_CLKSRC_IRC, /**< IRC 12 Mhz clock source */
CGU_CLKSRC_ENET_RX_CLK, /**< Ethernet receive clock source */
CGU_CLKSRC_ENET_TX_CLK, /**< Ethernet transmit clock source */
CGU_CLKSRC_GP_CLKIN, /**< General purpose clock source */
CGU_CLKSRC_TCK, /**< TCK clock source */
CGU_CLKSRC_XTAL_OSC, /**< Crystal oscillator clock source*/
CGU_CLKSRC_PLL0, /**< PLL0 (USB0) clock source */
CGU_CLKSRC_PLL0_AUDIO,
CGU_CLKSRC_PLL1, /**< PLL1 clock source */
CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3, /**< IDIVA clock source */
CGU_CLKSRC_IDIVB, /**< IDIVB clock source */
CGU_CLKSRC_IDIVC, /**< IDIVC clock source */
CGU_CLKSRC_IDIVD, /**< IDIVD clock source */
CGU_CLKSRC_IDIVE, /**< IDIVE clock source */
/* Base */
CGU_BASE_SAFE, /**< Base save clock (always on) for WDT */
CGU_BASE_USB0, /**< USB0 base clock */
CGU_BASE_USB1 = CGU_BASE_USB0 + 2, /**< USB1 base clock */
CGU_BASE_M3, /**< ARM Cortex-M3 Core base clock */
CGU_BASE_SPIFI, /**< SPIFI base clock */
//CGU_BASE_SPI,
CGU_BASE_PHY_RX = CGU_BASE_SPIFI + 2, /**< Ethernet PHY Rx base clock */
CGU_BASE_PHY_TX, /**< Ethernet PHY Tx base clock */
CGU_BASE_APB1, /**< APB peripheral block #1 base clock */
CGU_BASE_APB3, /**< APB peripheral block #3 base clock */
CGU_BASE_LCD, /**< LCD base clock */
CGU_BASE_ENET_CSR,
CGU_BASE_SDIO, /**< SDIO base clock */
CGU_BASE_SSP0, /**< SSP0 base clock */
CGU_BASE_SSP1, /**< SSP1 base clock */
CGU_BASE_UART0, /**< UART0 base clock */
CGU_BASE_UART1, /**< UART1 base clock */
CGU_BASE_UART2, /**< UART2 base clock */
CGU_BASE_UART3, /**< UART3 base clock */
CGU_BASE_CLKOUT, /**< CLKOUT base clock */
CGU_BASE_APLL = CGU_BASE_CLKOUT + 5,
CGU_BASE_OUT0,
CGU_BASE_OUT1,
CGU_ENTITY_NUM /**< Number or clock source entity */
} CGU_ENTITY_T;
/*
* @brief CGU PPL0 mode enumerate definition
*/
typedef enum {
CGU_PLL0_MODE_1d = 0,
CGU_PLL0_MODE_1c,
CGU_PLL0_MODE_1b,
CGU_PLL0_MODE_1a
}CGU_PLL0_MODE;
/*
* @brief CGU peripheral enumerate definition
*/
typedef enum {
CGU_PERIPHERAL_ADC0 = 0, /**< ADC0 */
CGU_PERIPHERAL_ADC1, /**< ADC1 */
CGU_PERIPHERAL_AES, /**< AES */
// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
CGU_PERIPHERAL_APB1_BUS, /**< APB1 bus */
CGU_PERIPHERAL_APB3_BUS, /**< APB3 bus */
CGU_PERIPHERAL_CAN, /**< CAN */
CGU_PERIPHERAL_CREG, /**< CREG */
CGU_PERIPHERAL_DAC, /**< DAC */
CGU_PERIPHERAL_DMA, /**< DMA */
CGU_PERIPHERAL_EMC, /**< EMC */
CGU_PERIPHERAL_ETHERNET, /**< Ethernet */
CGU_PERIPHERAL_ETHERNET_TX, //HIDE /**< Ethernet transmit */
CGU_PERIPHERAL_GPIO, /**< GPIO */
CGU_PERIPHERAL_I2C0, /**< I2C0 */
CGU_PERIPHERAL_I2C1, /**< I2C1 */
CGU_PERIPHERAL_I2S, /**< I2S */
CGU_PERIPHERAL_LCD, /**< LCD */
CGU_PERIPHERAL_M3CORE, /**< ARM Cortex-M3 Core */
CGU_PERIPHERAL_M3_BUS, /**< ARM Cortex-M3 Bus */
CGU_PERIPHERAL_MOTOCON, /**< Motor Control */
CGU_PERIPHERAL_QEI, /**< QEI */
CGU_PERIPHERAL_RITIMER, /**< RIT Timer */
CGU_PERIPHERAL_SCT, /**< SCT */
CGU_PERIPHERAL_SCU, /**< SCU */
CGU_PERIPHERAL_SDIO, /**< SDIO */
CGU_PERIPHERAL_SPIFI, /**< SPIFI */
CGU_PERIPHERAL_SSP0, /**< SSP0 */
CGU_PERIPHERAL_SSP1, /**< SSP1 */
CGU_PERIPHERAL_TIMER0, /**< TIMER 0 */
CGU_PERIPHERAL_TIMER1, /**< TIMER 1 */
CGU_PERIPHERAL_TIMER2, /**< TIMER 2 */
CGU_PERIPHERAL_TIMER3, /**< TIMER 3 */
CGU_PERIPHERAL_UART0, /**< UART0 */
CGU_PERIPHERAL_UART1, /**< UART1 */
CGU_PERIPHERAL_UART2, /**< UART2 */
CGU_PERIPHERAL_UART3, /**< UART3 */
CGU_PERIPHERAL_USB0, /**< USB0 */
CGU_PERIPHERAL_USB1, /**< USB1 */
CGU_PERIPHERAL_WWDT, /**< WWDT */
CGU_PERIPHERAL_NUM
} CGU_PERIPHERAL_T;
/**
* @brief CGU error status enumerate definition
*/
typedef enum {
CGU_ERROR_SUCCESS = 0,
CGU_ERROR_CONNECT_TOGETHER,
CGU_ERROR_INVALID_ENTITY,
CGU_ERROR_INVALID_CLOCK_SOURCE,
CGU_ERROR_INVALID_PARAM,
CGU_ERROR_FREQ_OUTOF_RANGE
} CGU_ERROR;
/********************************************************************//**
* @brief CGU structure definitions
**********************************************************************/
/*
* @brief CGU peripheral clock structure
*/
typedef struct {
uint8_t RegBaseEntity; /**< Base register address */
uint16_t RegBranchOffset; /**< Branch register offset */
uint8_t PerBaseEntity; /**< Base peripheral address */
uint16_t PerBranchOffset; /**< Base peripheral offset */
uint8_t next; /**< Pointer to next structure */
} CGU_PERIPHERAL_S;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup CGU_Public_Functions CGU Public Functions
* @{
*/
/** Clock generate initialize/de-initialize */
uint32_t CGU_Init(void);
uint32_t CGU_DeInit(void);
/** Clock Generator and Clock Control */
uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en);
uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock);
/** Clock Source and Base Clock operation */
uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency);
uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor);
uint32_t CGU_SetPLL0(void);
uint32_t CGU_SetPLL1(uint32_t mult);
uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en);
uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity);
uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base);
void CGU_UpdateClock(void);
uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_CGU_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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