Add GCC ARM Cortex-M4F MPU port.

Add RVDS ARM Cortex-M4F MPU port.
Increase the size of each buffer allocated to pbufs in the Microblaze lwIP demo to prevent pbufs chaining.
Use _start as the top of the stack for each Microblaze task, rather than NULL, as NULL was causing the Xilinx SDK to try and unwind the stack too far.

FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/GCC_Specific/sections.ld

@@ -5,22 +5,6 @@ MEMORY
   RAM (rw)         : ORIGIN = 0x20000000, LENGTH = 0x8000
 }
 
-/* Variables required by FreeRTOS MPU. */
-_Privileged_Functions_Region_Size = 16K;
-_Privileged_Data_Region_Size = 256;
-
-__FLASH_segment_start__ = ORIGIN( ROM );
-__FLASH_segment_end__ = __FLASH_segment_start__ + LENGTH( ROM );
-
-__privileged_functions_start__ = ORIGIN( ROM );
-__privileged_functions_end__ = __privileged_functions_start__ + _Privileged_Functions_Region_Size;
-
-__SRAM_segment_start__ = ORIGIN( RAM );
-__SRAM_segment_end__ = __SRAM_segment_start__ + LENGTH( RAM );
-
-__privileged_data_start__ = ORIGIN( RAM );
-__privileged_data_end__ = ORIGIN( RAM ) + _Privileged_Data_Region_Size;
-
 /* Variables used by FreeRTOS-MPU. */
 _Privileged_Functions_Region_Size = 16K;
 _Privileged_Data_Region_Size = 256;

FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwipopts.h

@@ -70,7 +70,7 @@ void vLwipAppsReleaseTxBuffer( void );
 #define LWIP_SO_RCVTIMEO		   		1
 #define LWIP_SO_RCVBUF			 		1
 
-#define LWIP_DEBUG
+#define NOT_LWIP_DEBUG
 #ifdef LWIP_DEBUG
 
 #define LWIP_DBG_MIN_LEVEL        LWIP_DBG_LEVEL_ALL // LWIP_DBG_LEVEL_SERIOUS
@@ -112,7 +112,7 @@ void vLwipAppsReleaseTxBuffer( void );
    byte alignment -> define MEM_ALIGNMENT to 2. */
 /* MSVC port: intel processors don't need 4-byte alignment,
    but are faster that way! */
-#define MEM_ALIGNMENT			4
+#define MEM_ALIGNMENT			64 /* For Eth lite. */
 
 /* MEM_SIZE: the size of the heap memory. If the application will send
 a lot of data that needs to be copied, this should be set high. */
@@ -159,8 +159,8 @@ a lot of data that needs to be copied, this should be set high. */
 /* MEMP_NUM_TCPIP_MSG_*: the number of struct tcpip_msg, which is used
    for sequential API communication and incoming packets. Used in
    src/api/tcpip.c. */
-#define MEMP_NUM_TCPIP_MSG_API   8
-#define MEMP_NUM_TCPIP_MSG_INPKT 8
+#define MEMP_NUM_TCPIP_MSG_API   16
+#define MEMP_NUM_TCPIP_MSG_INPKT 16
 
 #define MEMP_NUM_ARP_QUEUE		10
 
@@ -169,7 +169,7 @@ a lot of data that needs to be copied, this should be set high. */
 #define PBUF_POOL_SIZE			40
 
 /* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
-#define PBUF_POOL_BUFSIZE		512
+#define PBUF_POOL_BUFSIZE		1518 /* Max eth frame size so no chaining. */
 
 /* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
    link level header. */

FreeRTOS/Source/portable/Common/mpu_wrappers.c

@@ -337,7 +337,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 #endif
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
 	void MPU_vTaskList( char *pcWriteBuffer )
 	{
 	BaseType_t xRunningPrivileged = xPortRaisePrivilege();

FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c

@@ -384,7 +384,17 @@ BaseType_t xPortStartScheduler( void )
 	uxCriticalNesting = 0;
 
 	/* Start the first task. */
-	__asm volatile( "	svc %0			\n"
+	__asm volatile(
+					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
+					" ldr r0, [r0] 			\n"
+					" ldr r0, [r0] 			\n"
+					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
+					" cpsie i				\n" /* Globally enable interrupts. */
+					" cpsie f				\n"
+					" dsb					\n"
+					" isb					\n"
+					" svc %0				\n" /* System call to start first task. */
+					" nop					\n"
 					:: "i" (portSVC_START_SCHEDULER) );
 
 	/* Should not get here! */

FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c

@@ -99,6 +99,7 @@ FSR register is saved as part of the task context.  portINITIAL_FSR is the value
 given to the FSR register when the initial context is set up for a task being
 created. */
 #define portINITIAL_FSR				( 0U )
+
 /*-----------------------------------------------------------*/
 
 /*
@@ -150,6 +151,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 extern void *_SDA2_BASE_, *_SDA_BASE_;
 const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
 const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+extern void _start1( void );
 
 	/* Place a few bytes of known values on the bottom of the stack.
 	This is essential for the Microblaze port and these lines must
@@ -204,7 +206,7 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
 		pxTopOfStack--;
 		*pxTopOfStack = ( StackType_t ) 0x07;	/* R7 - other parameters and temporaries. */
 		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08;	/* R8 - other parameters and temporaries. */
+		*pxTopOfStack = ( StackType_t ) NULL;	/* R8 - other parameters and temporaries. */
 		pxTopOfStack--;
 		*pxTopOfStack = ( StackType_t ) 0x09;	/* R9 - other parameters and temporaries. */
 		pxTopOfStack--;
@@ -222,7 +224,7 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
 	pxTopOfStack--;
 	*pxTopOfStack = ( StackType_t ) pxCode;	/* R14 - return address for interrupt. */
 	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) NULL;	/* R15 - return address for subroutine. */
+	*pxTopOfStack = ( StackType_t ) _start1;	/* R15 - return address for subroutine. */
 
 	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
 		pxTopOfStack--;