Update Zynq MPSoC hardware definition and BSP files to be those shipped with the 2016.4 SDK.
This commit is contained in:
Richard Barry
@ -56,7 +56,7 @@
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<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
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</option>
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<option id="xilinx.gnu.c.linker.option.lscript.210457854" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
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<option id="xilinx.gnu.c.link.option.other.791632065" name="Other options (-XLinker [option])" superClass="xilinx.gnu.c.link.option.other" valueType="stringList"/>
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<option id="xilinx.gnu.c.link.option.other.791632065" name="Other options (-XLinker [option])" superClass="xilinx.gnu.c.link.option.other"/>
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<inputType id="xilinx.gnu.linker.input.294386883" superClass="xilinx.gnu.linker.input">
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<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
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<additionalInput kind="additionalinput" paths="$(LIBS)"/>
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@ -1,8 +1,8 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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<storageModule moduleId="org.eclipse.cdt.core.settings">
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<cconfiguration id="org.eclipse.cdt.core.default.config.691372241">
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<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.691372241" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
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<cconfiguration id="org.eclipse.cdt.core.default.config.1652171495">
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<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1652171495" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
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<externalSettings/>
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<extensions/>
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</storageModule>
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@ -1,7 +1,7 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<projectDescription>
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<name>RTOSDemo_A53_bsp</name>
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<comment>Created by SDK v2016.1</comment>
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<comment>Created by SDK v2016.4</comment>
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<projects>
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</projects>
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<buildSpec>
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File diff suppressed because it is too large
Load Diff
@ -166,7 +166,7 @@ s32 XCanPs_SelfTest(XCanPs *InstancePtr)
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for (Index = 0U; Index < 8U; Index++) {
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if(*FramePtr != 0U) {
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*FramePtr = (u8)Index;
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*FramePtr++;
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FramePtr++;
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}
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}
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@ -1,6 +1,6 @@
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/******************************************************************************
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*
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* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
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* Copyright (C) 2015-2016 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -51,12 +51,18 @@
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* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
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* kvn 08/18/15 Modified Makefile according to compiler changes.
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* 1.2 kvn 10/09/15 Add support for IAR Compiler.
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* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
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* for MB BSPs. Instead it throws up a warning. This
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* fixes the CR#953056.
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*
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#ifdef __MICROBLAZE__
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#warning "The driver is supported only for ARM architecture"
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#else
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#include <xil_types.h>
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#include <xpseudo_asm.h>
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@ -177,5 +183,6 @@ static INLINE u32 XCoresightPs_DccGetStatus(void)
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}
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#endif
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return Status;
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#endif
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}
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/** @} */
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@ -55,16 +55,20 @@
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* 1.00 kvn 02/14/15 First release
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* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
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* kvn 08/18/15 Modified Makefile according to compiler changes.
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* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
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* for MB BSPs. Instead it throws up a warning. This
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* fixes the CR#953056.
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*
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#ifndef __MICROBLAZE__
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#include <xil_types.h>
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void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
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u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
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#endif
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/** @} */
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@ -46,6 +46,8 @@
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* Ver Who Date Changes
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* ----- ------ -------- ---------------------------------------------------
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* 1.0 vnsld 22/10/14 First release
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* 1.1 adk 10/05/16 Fixed CR#951040 race condition in the recv path when
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* source and destination points to the same buffer.
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* </pre>
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*
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******************************************************************************/
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@ -152,8 +154,12 @@ void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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}
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/* Invalidating cache memory */
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else {
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#if defined(__aarch64__)
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Xil_DCacheInvalidateRange(Addr, Size <<
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(u32)(XCSUDMA_SIZE_SHIFT));
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#else
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Xil_DCacheFlushRange(Addr, Size << (u32)(XCSUDMA_SIZE_SHIFT));
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#endif
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}
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XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
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@ -97,6 +97,8 @@
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* Ver Who Date Changes
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* ----- ------ -------- -----------------------------------------------------
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* 1.0 vnsld 22/10/14 First release
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* 1.1 adk 10/05/16 Fixed CR#951040 race condition in the recv path when
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* source and destination points to the same buffer.
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* </pre>
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*
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******************************************************************************/
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