perfmon: show distribution of uops delivered to frontend
Breakdown the distribution of uops delivered to the frontend. Collerates directly with the source of the uops. Type: improvement Signed-off-by: Ray Kinsella <mdr@ashroe.eu> Change-Id: I93a57dbe56dfa0f378527844aa4e63f45a548e55
This commit is contained in:

committed by
Damjan Marion

parent
502714fc44
commit
489d89c1cb
@ -34,7 +34,8 @@ add_vpp_plugin(perfmon
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intel/bundle/topdown_metrics.c
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intel/bundle/topdown_icelake.c
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intel/bundle/topdown_tremont.c
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intel/bundle/frontend_bound_bw.c
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intel/bundle/frontend_bound_bw_src.c
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intel/bundle/frontend_bound_bw_uops.c
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intel/bundle/frontend_bound_lat.c
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intel/bundle/iio_bw.c
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@ -25,7 +25,7 @@ enum
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};
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static u8 *
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format_intel_frontend_bound_bw (u8 *s, va_list *args)
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format_intel_frontend_bound_bw_src (u8 *s, va_list *args)
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{
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perfmon_node_stats_t *ss = va_arg (*args, perfmon_node_stats_t *);
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int row = va_arg (*args, int);
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@ -65,12 +65,12 @@ format_intel_frontend_bound_bw (u8 *s, va_list *args)
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return s;
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}
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static perfmon_cpu_supports_t frontend_bound_bw_cpu_supports[] = {
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static perfmon_cpu_supports_t frontend_bound_bw_cpu_supports_src[] = {
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{ clib_cpu_supports_avx512_bitalg, PERFMON_BUNDLE_TYPE_NODE },
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};
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PERFMON_REGISTER_BUNDLE (intel_core_frontend_bound_bw) = {
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.name = "td-frontend-bw",
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PERFMON_REGISTER_BUNDLE (intel_core_frontend_bound_bw_src) = {
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.name = "td-frontend-bw-src",
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.description =
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"Topdown FrontEnd-bound BandWidth - % uops from each uop fetch source",
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.source = "intel-core",
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@ -79,9 +79,9 @@ PERFMON_REGISTER_BUNDLE (intel_core_frontend_bound_bw) = {
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.events[2] = INTEL_CORE_E_IDQ_MITE_UOPS, /* 0x0F */
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.events[3] = INTEL_CORE_E_LSD_UOPS, /* 0x0F */
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.n_events = 4,
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.format_fn = format_intel_frontend_bound_bw,
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.cpu_supports = frontend_bound_bw_cpu_supports,
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.n_cpu_supports = ARRAY_LEN (frontend_bound_bw_cpu_supports),
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.format_fn = format_intel_frontend_bound_bw_src,
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.cpu_supports = frontend_bound_bw_cpu_supports_src,
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.n_cpu_supports = ARRAY_LEN (frontend_bound_bw_cpu_supports_src),
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.column_headers = PERFMON_STRINGS ("UOPs/PKT", "% DSB UOPS", "% MS UOPS",
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"% MITE UOPS", "% LSD UOPS"),
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.footer =
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89
src/plugins/perfmon/intel/bundle/frontend_bound_bw_uops.c
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89
src/plugins/perfmon/intel/bundle/frontend_bound_bw_uops.c
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@ -0,0 +1,89 @@
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/*
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* Copyright (c) 2022 Intel and/or its affiliates.
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <perfmon/perfmon.h>
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#include <perfmon/intel/core.h>
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enum
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{
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THREAD_P,
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THREE_UOP,
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TWO_UOP,
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ONE_UOP,
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NO_UOP,
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FOUR_UOP,
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};
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static u8 *
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format_intel_frontend_bound_bw_uops (u8 *s, va_list *args)
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{
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perfmon_node_stats_t *ss = va_arg (*args, perfmon_node_stats_t *);
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int row = va_arg (*args, int);
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f64 sv = 0;
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f64 cycles = ss->value[THREAD_P];
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switch (row)
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{
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case 0:
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sv = (ss->value[FOUR_UOP] / cycles) * 100;
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break;
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case 1:
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sv = ((ss->value[THREE_UOP] - ss->value[TWO_UOP]) / cycles) * 100;
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break;
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case 2:
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sv = ((ss->value[TWO_UOP] - ss->value[ONE_UOP]) / cycles) * 100;
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break;
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case 3:
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sv = ((ss->value[ONE_UOP] - ss->value[NO_UOP]) / cycles) * 100;
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break;
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case 4:
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sv = (ss->value[NO_UOP] / cycles) * 100;
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break;
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}
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s = format (s, "%04.1f", sv);
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return s;
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}
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static perfmon_cpu_supports_t frontend_bound_bw_cpu_supports_uops[] = {
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{ clib_cpu_supports_avx512_bitalg, PERFMON_BUNDLE_TYPE_NODE },
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};
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PERFMON_REGISTER_BUNDLE (intel_core_frontend_bound_bw_uops) = {
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.name = "td-frontend-bw-uops",
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.description = "Topdown FrontEnd-bound BandWidth - distribution of "
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"uops delivered to frontend",
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.source = "intel-core",
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.events[0] = INTEL_CORE_E_CPU_CLK_UNHALTED_THREAD_P, /* 0x0F */
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.events[1] =
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INTEL_CORE_E_IDQ_UOPS_NOT_DELIVERED_CYCLES_3_UOP_DELIV_CORE, /* 0xFF */
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.events[2] =
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INTEL_CORE_E_IDQ_UOPS_NOT_DELIVERED_CYCLES_2_UOP_DELIV_CORE, /* 0xFF */
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.events[3] =
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INTEL_CORE_E_IDQ_UOPS_NOT_DELIVERED_CYCLES_1_UOP_DELIV_CORE, /* 0xFF */
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.events[4] =
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INTEL_CORE_E_IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOP_DELIV_CORE, /* 0xFF */
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.events[5] = INTEL_CORE_E_IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK, /* 0xFF */
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.n_events = 6,
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.format_fn = format_intel_frontend_bound_bw_uops,
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.cpu_supports = frontend_bound_bw_cpu_supports_uops,
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.n_cpu_supports = ARRAY_LEN (frontend_bound_bw_cpu_supports_uops),
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.column_headers = PERFMON_STRINGS ("% 4 UOPS", "% 3 UOPS", "% 2 UOPS",
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"% 1 UOPS", "% 0 UOPS"),
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.footer =
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"For more information, see the Intel(R) 64 and IA-32 Architectures\n"
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"Optimization Reference Manual section on the Front End.",
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};
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@ -152,6 +152,17 @@
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_ (0x9C, 0x01, 0, 0, 0, 0x05, IDQ_UOPS_NOT_DELIVERED, CORE, \
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"Uops not delivered to Resource Allocation Table (RAT) per thread when " \
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"backend of the machine is not stalled") \
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_ (0x9C, 0x01, 0, 0, 1, 0x01, IDQ_UOPS_NOT_DELIVERED, CYCLES_FE_WAS_OK, \
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"Cycles with 4 uops delivered by the front end or Resource Allocation " \
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"Table (RAT) was stalling FE.x") \
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_ (0x9C, 0x01, 0, 0, 0, 0x01, IDQ_UOPS_NOT_DELIVERED_CYCLES_3_UOP_DELIV, \
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CORE, "Cycles with 3 uops delivered by the front end.") \
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_ (0x9C, 0x01, 0, 0, 0, 0x02, IDQ_UOPS_NOT_DELIVERED_CYCLES_2_UOP_DELIV, \
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CORE, "Cycles with 2 uops delivered by the front end.") \
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_ (0x9C, 0x01, 0, 0, 0, 0x03, IDQ_UOPS_NOT_DELIVERED_CYCLES_1_UOP_DELIV, \
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CORE, "Cycles with 1 uops delivered by the front end.") \
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_ (0x9C, 0x01, 0, 0, 0, 0x04, IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOP_DELIV, \
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CORE, "Cycles with 0 uops delivered by the front end.") \
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_ (0xA1, 0x01, 0, 0, 0, 0x00, UOPS_DISPATCHED, PORT_0, \
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"Number of uops executed on port 0") \
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_ (0xA1, 0x02, 0, 0, 0, 0x00, UOPS_DISPATCHED, PORT_1, \
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