vppinfra: SFENCE requires SSE2 to be enabled

Change-Id: I0469bb91107cf0acced3cd19820db8d3712701c0
Type: fix
Fixes: eaabe07
Signed-off-by: Damjan Marion <damarion@cisco.com>
This commit is contained in:
Damjan Marion
2023-04-17 14:11:57 +00:00
committed by Florin Coras
parent 6a1a832346
commit 687823f017

View File

@ -181,7 +181,7 @@
/* Full memory barrier (read and write). */
#define CLIB_MEMORY_BARRIER() __sync_synchronize ()
#if __x86_64__
#if __SSE__
#define CLIB_MEMORY_STORE_BARRIER() __builtin_ia32_sfence ()
#else
#define CLIB_MEMORY_STORE_BARRIER() __sync_synchronize ()